ALTERNATIVE
In some applications, a full scale of 10.24 V (for an LSB of
2.5 mV) or 20.48 V (for an LSB of 5.0 mV) is more convenient.
In the unipolar mode of operation, replace R2 with a 200
Ω
potentiometer and add 150
Ω
in series with the 10 V IN pin for
10.24 V input range or 500
Ω
in series with the 20 V IN pin for
20.48 V input range. In bipolar mode of operation, replace R1
with a 500
Ω
potentiometer (in addition to the previous
changes). The calibration will remain similar to the standard
calibration procedure.
Figure 7 - Interfacing the SPT774 to an 8-Bit Data Bus
Ao
Address Bus
~
STS
12/8
MSB
Ao
Data
Bus
CONTROLLING THE SPT774
The SPT774 can be operated by most microprocessor sys-
tems due to the control input pins and on-chip logic. It may
also be operated in the stand-alone mode and enabled by the
R/
C
input pin. Full
µP
control consists of selecting an 8 or
12-bit conversion cycle, initiating the conversion, and reading
the output data when ready. The output read has the options
of choosing either 12-bits at once or 8 bits followed by
4-bits in a left-justified format. All five control inputs are TTL/
CMOS compatible and include 12/
8
,
CS
, Ao, R/
C
and CE.
The use of these inputs in controlling the converter’s opera-
tions is shown in table I, and the internal control logic is shown
in a simplified schematic in figure 10.
STAND-ALONE OPERATION
The simplest interface is a control line connected to R/
C
. The
output controls must be tied to known states as follows: CE
and 12/
8
are wired high, Ao and
CS
are wired low. The output
data arrives in words of 12-bits each. The limits on R/
C
duty
cycle are shown in figures 3 and 4. It may have a duty cycle
within and including the extremes shown in the specifica-
tions. In general, data may be read when R/
C
is high unless
STS is also high, indicating a conversion is in progress.
Table I - Truth Table for the SPT774 Control Inputs
CE
0
X
CS
X
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
R/C
X
X
0
0
0
0
12/8
X
X
X
X
X
X
X
X
1
0
0
Ao
X
X
0
1
0
1
0
1
X
0
1
Operation
None
None
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Initiate 12 bit conversion
Initiate 8 bit conversion
Enable 12 bit Output
Enable 8 MSB's Only
Enable 4 LSB's Plus 4
Trailing Zeroes
LSB
DIG
COM
CONTROLLED OPERATION
CONVERSION LENGTH
A conversion start transition latches the state of Ao as shown
in figure 7 and table I. The latched state determines if the
conversion stops with 8 bits (Ao high) or continues for 12 bits
(Ao low). If all 12 bits are read following an 8-bit conversion, the
three LSBs will be a logic 0 and DB3 will be a logic 1. Ao is latched
because it is also involved in enabling the output buffers as
will be explained later. No other control inputs are latched.
CONVERSION START
A conversion may be initiated by a logic transition on any of
the three inputs: CE,
CS
, R/
C
, as shown in table I. The last
of the three to reach the correct state starts the conversions,
so one, two or all three may be dynamically controlled. The
nominal delay from each is the same and all three may
change state simultaneously. In order to assure that a par-
ticular input controls the start of conversion, the other two
should be set up at least 50 ns earlier. Refer to the convert
mode timing specifications. The Convert Start timing diagram
is illustrated in figure 1.
The output signal STS is the status flag and goes high only
when a conversion is in progress. While STS is high, the
output buffers remain in a high impedance state so that data
can not be read. Also, when STS is high, an additional Start
Convert will not reset the converter or reinitiate a conversion.
Note, if Ao changes state after a conversion begins, an
additional Start Convert command will latch the new start of
Ao and possibly cause a wrong cycle length for that conver-
sion (8 versus 12 bits).
SPT774
8
8/1/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
