GENERAL OVERVIEW
The SPT7610 is an ultra high-speed monolithic 6-bit
parallel flash A/D converter. The nominal conversion rate
is 1 GSPS, and the analog bandwidth is typically 1.4 GHz.
A major advance over previous flash converters is the
inclusion of 64 input preamplifiers between the reference
ladder and input comparators. (See the block diagram.)
This not only reduces clock transient kickback to the input
and reference ladder due to a low AC beta but also
reduces the effect of the dynamic state of the input signal
on the latching characteristics of the input comparators.
The preamplifiers act as buffers and stabilize the input
capacitance so that it remains constant over different
input voltage and frequency ranges. This makes the part
easier to drive than previous flash converters. The pre-
amplifiers also add a gain of two to the input signal so that
each comparator has a wider overdrive or threshold range
to “trip” into or out of the active state. This gain reduces
metastable states that can cause errors at the output.
The SPT7610 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise. Signature errors are also
reduced by careful layout of the analog circuitry. The out-
put drive capability of the device can provide full ECL
swings into 50
Ω
loads.
Only one –5.2 V power supply is required. Two external
references are applied across the internal reference lad-
der that has a resistance of 80
Ω
typical (60
Ω
minimum).
The top reference is typically 0 V or connected to AGND
(analog ground). The device has top force and sense pins
(V
RFT
and V
RST
) that are internally connected together.
These voltage force and sense pins can be used to mini-
mize the voltage drop across the parasitic line resistance.
The bottom reference is typically –1 V. The device also has
bottom force and sense pins (V
RFB
and V
RSB
) that are
internally connected together. These can also be used to
minimize the voltage drop across the parasitic line resis-
tance. Three additional reference taps (V
R3
= –0.25 V typ,
V
RM
= –0.5 V typ, and V
R1
= –0.75 V typ) are brought out.
These taps can be used to control the linearity error.
All logic levels are compatible with both 10K ECL or 100K
ECL. It is recommended that the clock input be driven
differentially (CLK and NCLK) to improve noise immunity
and reduce aperture jitter.
The digital outputs are split into two banks of 6-bit words
and an overrange bit. Each bank is updated at 1/2 of the
clock rate and is 180° out of phase from the other. The dif-
ferential data ready signals for each bank are provided to
accurately latch each data bank into the register. The out-
put data is in a straight binary, inverted binary, two’s
complement or inverted two’s complement format. Figure
1 shows a timing diagram of the device and shows the in-
put-to-output relationship, clock-to-output delay and out-
put latency. The SPT7610 has a built-in offset in the ÷2
clock divider (D Flip-Flop) to assure that output bank A will
come up first after power turn on.
SPT7610
4
1/21/02
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
