around 300 MHz, the amplifier’s phase crossover point. The
unity-gain bandwidth is roughly 700 MHz. Larger value
capacitors exhibit lower self-resonance frequency and thus
may not adequately compensate the reference amplifier.
Large capacitors may also introduce low frequency tails
which increase settling time. The DAC itself exhibits very
broadband switching spikes (charge kickback) at the R
SET
node, which can contribute to amplifier instability if not sup-
pressed. Note that the AMP
INB
input must not be directly
bypassed, as this will short all feedback to ground, leading
to severe oscillation.
Compensation must be optimized for each application. As
with any high-speed, high-resolution design, attention must
be paid to grounding, decoupling, and parasitic elements
that may cause instability. It may be wise to use a guard
ring, and/or clear the board ground, around the reference
amplifier’s inputs. All traces must be short, and capacitors
with high self-resonance must be used.
Compensation is perhaps the most challenging aspect of
setting up the SPT5510. By slowly switching a full-scale
data input (generating a low-frequency square wave), with
appropriate clock timing, the DAC’s output can be observed
using a suitable oscilloscope and spectrum analyzer to
observe and suppress any oscillations caused by board and
decoupling parasitics. Consult CADEKA Applications for fur-
ther assistance if required.
LONG-TERM STABILITY
VERSUS TEMPERATURE
As with all high-speed, high-resolution digital-to-analog con-
verters, the initial accuracy of the device will degrade with
both time and temperature. The graph shown in figure 7 can
be used to determine the expected change in linearity per-
formance over time when the device is operated at various
ambient temperatures. This graph shows how long it will
take for the SPT5510 linearity to change by 8 ppm (or 1/2
LSB) at any operating temperature. The top curve shown
represents integral nonlinearity (ILE) changes; the bottom
curve shows differential nonlinearity (DLE) changes.
Figure 7 – Linearity Performance over Time
1000 years
100 years
(Hours)
1 year
10
4
10
5
10
6
10
7
ILE
10
3
1 month
DLE
10
2
0
20
40
60
80
100
120
Temperature (°C)
Expected time required to produce an 8 ppm (1/2 LSB) linearity
(ILE or DLE) shift as a function of temperature.
PACKAGE OUTLINE
44-Lead MQFP
A
B
SYMBOL
A
Pin 1
Index
INCHES
MIN
MAX
0.5098
0.3917
0.3917
0.5098
0.0311
0.0118
0.0768
0.0039
0.0287
0.5295
0.3957
0.3957
0.5295
0.0319
0.0177
0.0827
0.0098
0.0406
MILLIMETERS
MIN
MAX
12.95
9.95
9.95
12.95
0.79
0.30
1.95
0.10
0.73
13.45
10.05
10.05
13.45
0.81
0.45
2.10
0.25
1.03
1.60 REF
0°
7°
B
C
D
C
D
E
F
G
H
E
F
I
J
0.0630 REF
0°
7°
G
I
H
J
K
K
SPT5510
7
9/27/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
