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SPT5510SIM 参数 Datasheet PDF下载

SPT5510SIM图片预览
型号: SPT5510SIM
PDF下载: 下载PDF文件 查看货源
内容描述: 16 - BIT , 200 MWPS ECL D / A转换器 [16-BIT, 200 MWPS ECL D/A CONVERTER]
分类和应用: 转换器
文件页数/大小: 8 页 / 165 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
Supply Voltages
Negative supply voltage (V
EE
) ................................. –7 V
A/D ground voltage differential ................................ 0.5 V
Input Voltages
Digital input voltage (D15–D0, Clock)... ........... –2.5 to 0 V
Ref amp input voltage range .......................... –2.5 to 0 V
Reference input voltage range (Ref In) ...... V
EE
to –2.5 V
Output Currents
Bandgap reference output current .....................
±500 µA
Ref amplifier output current ................................
±2.5
mA
Temperature
Operating temperature ............................... –40 to +85
°C
Junction temperature .......................................... +150
°C
Lead, soldering (10 seconds) ............................. +250
°C
Storage .................................................... –65 to +150
°C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for nominal operating
conditions.
ELECTRICAL SPECIFICATIONS
T
A
= 25
°C,
V
EE
=–5.2 V
±5%,
50% duty cycle clock, unless otherwise specified.
PARAMETERS
DC Performance
1
Resolution
Differential Linearity
Differential Linearity
Integral Linearity
Integral Linearity
Integral Linearity Drift
Offset Drift
Monotonicity
Output Capacitance
Gain Error
Gain Error Tempco
Gain Error Tempco
Offset Error
Compliance Voltage
Output Resistance
Dynamic Performance
Conversion Rate
Settling Time t
ST2
TEST
CONDITIONS
TEST
LEVEL
MIN
SPT5510
TYP
16
±0.6
±1.0
±0.75
±1.5
MAX
UNITS
Bits
LSB
LSB
LSB
LSB
LSB/°C
ppm FS/°C
Bits
pF
% FS
ppm FS/°C
ppm FS/°C
µA
V
kΩ
MHz
T
MIN
–T
MAX
T
MIN
–T
MAX
T
MIN
–T
MAX
With Ext Reference
With Internal Bandgap Ref
VI
IV
VI
IV
IV
IV
V
V
I
V
V
I
IV
IV
IV
–1.95
–4.0
–1.95
–4.0
–0.2
–2.5
15
–2
1.95
4.0
1.95
4.0
0.2
2.5
10
0.4
50
50
2
–4
–1.2
0.88
200
1.1
4
2
1.32
Settling to
±0.01%
Settling to
±0.0008%
Delay Time t
D
Glitch Energy
Full Scale Output Current
Rise Time/Fall Time
Spurious Free Dynamic Range
ƒ
OUT
=5 MHz; ƒ
CLOCK
=30 MHz
ƒ
OUT
=10 MHz; ƒ
CLOCK
=100 MHz
1
Measured
With On-Chip References
R
L
= 50
10 MHz Span
10 MHz Span
V
V
V
V
V
V
V
V
25
35
2
30
19
2
84
76
ns
ns
ns
pV-s
mA
ns
dB
dB
at 0 V output using I-V.
2
Measured as voltage settling for mid-scale transition; R
L
= 50
Ω.
SPT5510
2
9/27/00