Data Sheet
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
D
2.5
2
SOIC-14
P = P
- P
load
D
supply
1.5
1
Supply power is calculated by the standard power equa-
tion.
SOIC-8
P
= V
× I
supply
supply RMS supply
0.5
0
V
= V - V
S+ S-
supply
Power delivered to a purely resistive load is:
-40
-20
0
20
40
60
80
2
P
= ((V
)
)/Rload
eff
load
LOAD RMS
Ambient Temperature (°C)
The effective load resistor (Rload ) will need to include
eff
the effect of the feedback network. For instance,
Figure 8. Maximum Power Derating
Rload in figure 3 would be calculated as:
eff
R || (R + R )
Better thermal ratings can be achieved by maximizing PC
board metallization at the package pins. However, be care-
ful of stray capacitance on the input pins.
L
f
g
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load In addition, increased airflow across the package can also
impedance is needed to determine the dissipated power. help to reduce the effective Ө of the package.
JA
Here, P can be found from
D
In the event the outputs are momentarily shorted to a low
impedance path, internal circuitry and output metallization
are set to limit and handle up to 65mA of output current.
However, extended duration under these conditions may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded.
P = P
+ P
- P
D
Quiescent
Dynamic Load
Quiescent power can be derived from the specified I val-
ues along with known supply voltage, V
can be calculated as above with the desired signal ampli-
tudes using:
S
. Load power
Supply
Layout Considerations
(V
)
= V
/ √2
LOAD RMS
PEAK
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Assuming the load is referenced in the middle of the power
rails or V /2.
supply
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
Figure 8 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8 and 14 lead
SOIC packages.
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
©2004-2008 CADEKA Microcircuits LLC
www.cadeka.com
12
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
