Data Sheet
Input Voltage (0.5V/div)
Input
R
L
= 2kΩ
V
in
=2V
pp
G=5
R
f
= 1kΩ
Output
Refer to the evaluation board layouts shown in Figure 7
for more information.
When evaluating only one channel, complete the following
on the unused channel:
1. Ground the non-inverting input.
2. Short the output to the inverting input.
Comlinear CLC2005
Dual, Low Cost, +2.7V to 5.5V, 260MHz Rail-to-Rail Amplifier
Evaluation Board Information
Time (20ns/div)
Figure 4: Overdrive Recovery
The following evaluation boards are available to aid in the
testing and layout of this device:
Eval Board
CEB006
Description
Dual Channel, Dual Supply
8 lead SOIC
Products
CLC2005SO8
®
Driving Capacitive Loads
The
Frequency Response vs. C
L
plot on page 6, illustrates
the response of the CLC2005. A small series resistance
(R
s
) at the output of the amplifier, illustrated in Figure 5,
will improve stability and settling performance. R
s
values
in the
Frequency Response vs. C
L
plot were chosen to
achieve maximum bandwidth with less than 1dB of peak-
ing. For maximum flatness, use a larger R
s
.
+
-
R
g
R
f
Evaluation board schematics and layouts are shown in
Figure 6 and Figure 7.
The CEB006 evaluation board is built for dual supply
operation. Follow these steps to use the board in a single
supply application:
1. Short -V
s
to ground.
2. Use C3 and C4, if the -V
s
pin of the CLC2005 is
not directly connected to the ground plane.
R
s
C
L
R
L
Figure 5: Typical Topology for driving a capacitive load
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. Cadeka has evaluation
boards to use as a guide for high frequency layout and to
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
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n
Include 6.8μF and 0.1μF ceramic capacitors
Place the 6.8μF capacitor within 0.75 inches of the
power pin
Place the 0.1μF capacitor within 0.1 inches of the
power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
Figure 6: Evaluation Board Schematic
www.cadeka.com
Rev 1B
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n
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©2004-2009 CADEKA Microcircuits LLC
11
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
