Data Sheet
reducing R will increase bandwidth at the expense of ad-
ditional overshoot and ringing.
2.5
2
S
SOIC-16
Overdrive Recovery
1.5
1
SOT23-6
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx004 will typically recover in less
than 20ns from an overdrive condition. Figure 5 shows the
CLC1004 in an overdriven condition.
0.5
SOT23-5
0
-40
-20
0
20
40
60
80
Ambient Temperature (°C)
Figure 3. Maximum Power Derating
3
2
3
VIN = 2.5Vpp
G = 5
Driving Capacitive Loads
2
Input
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
1
1
0
0
Output
R , between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 4.
S
-1
-2
-3
-1
-2
-3
Input
+
-
Rs
Output
0
20
40
60
80
100 120 140 160 180 200
CL
RL
T im e ( n s )
Rf
Rg
Figure 5. Overdrive Recovery
Figure 4. Addition of R for Driving
Layout Considerations
S
Capacitive Loads
General layout and supply bypassing play major roles
in high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
Table 1 provides the recommended R for various capaci-
S
tive loads. The recommended R values result in <=1dB
S
peaking in the frequency response. The Frequency Re-
sponse vs. C plots, on page 7, illustrates the response of
L
the CLCx004.
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
C (pF)
L
R (Ω)
S
-3dB BW (MHz)
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
20
50
20
15
10
5
400
270
195
80
100
500
1000
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
3.3
58
• Minimize all trace lengths to reduce series inductances
Table 1: Recommended R vs. C
S
L
Refer to the evaluation board layouts below for more in-
For a given load capacitance, adjust R to optimize the
S
formation.
tradeoff between settling time and bandwidth. In general,
©2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
16
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
