PRELIMINARY
Data Sheet
Pin Configuration
TQFP-64
D0_5
D0_4
D0_3
CDK2308
Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
1
2
3
4
5
6
7
8
9
10
11
12
DVSSCLK
DVDDCLK
CLKP
CLKN
49
48
47
46
45
44
N/C
N/C
N/C
CLK_EXT
CDK2308
TQFP-64
43
42
41
40
39
38
37
36
35
34
33
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
N/C
N/C
Pin Assignments
Pin No.
1, 18, 23
2
3, 9, 12
4, 5, 8
6, 7
10, 11
13
14
15
16
17, 64
19
20
21
22
24, 41, 58
25, 40, 57
26
Pin Name
DV
DD
CM_EXT
AV
DD
AV
SS
IP0, IN0
IP1, IN1
DV
SSCLK
DV
DDCLK
CLKP
CLKN
DV
SS
CLK_EXT_EN
D
FRMT
PD_N
OE_N_1
O
VDD
O
VSS
NC
Description
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
Analog supply voltage, 1.8V
Analog ground
Analog input Channel 0 (non-inverting, inverting)
Analog input Channel 1 (non-inverting, inverting)
Clock circuitry ground
Clock circuitry supply voltage, 1.8V
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, bypass CLKN to ground with a 10nF capacitor
Digital circuitry ground
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero.
Output Enable Channel 0. Tristate when high
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
No Connect
CLK_EXT_EN
N/C
Rev 0.1.1
©2008 CADEKA Microcircuits LLC
www.cadeka.com
2
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
