PRELIMINARY
Data Sheet
Electrical Characteristics - CDK2308D
(AV
DD
=1.8V, DV
DD
=1.8V, DV
DDCLK
=1.8V, OV
DD
=2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
13-bit output, unless otherwise noted)
symbol
Performance
Parameter
conditions
F
IN
= 8MHz
Min
typ
61.6
61.2
61.3
61.3
61.3
60.7
61.0
58.7
74.8
73.9
74.7
61.7
-88.5
-95.0
-88.9
-79.0
-74.8
-75.0
-74.7
-61.7
9.9
9.8
9.8
9.5
-95.0
Max
units
CDK2308
Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
bits
bits
dBc
SNR
Signal to Noise Ratio
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
= FS / 2
F
IN
= 8MHz
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
= FS / 2
F
IN
= 8MHz
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
= FS / 2
F
IN
= 8MHz
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
= FS / 2
F
IN
= 8MHz
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
= FS / 2
F
IN
= 8MHz
F
IN
= 20MHz
F
IN
= 30MHz
F
IN
= FS / 2
Signal crosstalk between channels, F
IN1
=
8MHz, F
IN0
= 9.9MHz
SNDR
Signal to Noise and Distortion Ratio
SFDR
Spurious Free Dynamic Range
HD2
Second order Harmonic Distortion
HD3
Third order Harmonic Distortion
ENOB
Effective number of Bits
X
TALK
Crosstalk
Power Supply
AI
DD
DI
DD
Analog Supply Current
Digital Supply Current
Digital core supply
2.5V output driver supply, sine wave input,
F
IN
= 1MHz
2.5V output driver supply, sine wave input,
F
IN
= 1MHz, CLK_EXT disabled
OV
DD
= 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
OV
DD
= 2.5V, 5pF load on output bits,
F
IN
= 1MHz, CLK_EXT disabled
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
80
65
26.5
6.1
9.5
7.6
47.7
30.0
77.7
9.1
46.1
18.3
mA
mA
mA
mA
mW
mW
mW
µW
mW
mW
MSPS
MSPS
OI
DD
Output Driver Supply
Analog Power Dissipation
Digital Power Dissipation
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
Sleep Mode 2
Rev 0.1.1
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
©2008 CADEKA Microcircuits LLC
www.cadeka.com
9
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
