CDK2307 参数 Datasheet PDF下载

Data Sheet

Electrical Characteristics

(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,

-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)

Symbol

DC Accuracy

Parameter

No Missing Codes

Offset Error

Gain Error

Gain Matching

Conditions

Min

Typ

Guaranteed

Max

Units

CDK2307

Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

Midscale offset

Full scale range deviation from typical

Gain matching between channels. ±3 sigma

value at worst case conditions.

12-bit level

12-bit level

-6

1

6

±0.5

±0.2

±0.6

VAVDD/2

LSB

%FS

%FS

LSB

LSB

V

V

CM

+0.2

V

Vpp

Vpp

pF

MHz

DNL

INL

V

CMO

Differential Non-Linearity

Integral Non-Linearity

Common Mode Voltage Output

Input Common Mode

Full Scale Range, Normal

Analog Input

V

CMI

V

FSR

Analog input common mode voltage

Differential input voltage range,

Differential input voltage range, 1V

(see section Reference Voltages)

Differential input capacitance

Input bandwidth, full power

Supply voltage to all 1.8V domain pins.

See Pin Configuration and Description

Output driver supply voltage (OVDD).

Must be higher than or equal to Core Supply

Voltage (VOVDD

≥

VDVDD)

500

1.7

1.7

1.8

2.5

2.0

3.6

V

CM

-0.1

2.0

1.0

2.0

Full Scale Range, Option

Input Capacitance

Bandwidth

Power Supply

AVDD, DVDD

OVDD

Core Supply Voltage

I/O Supply Voltage

V

V

Rev 2A

©2009 CADEKA Microcircuits LLC

www.cadeka.com

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