ADVANCE Data Sheet
tributes to the Power Down Dissipation. The startup time
from this mode is longer than for Sleep Mode as all refer-
ences need to settle to their final values before normal
operation can resume.
Reference Voltages
The reference voltages are internally generated and buff-
ered based on a bandgap voltage reference. No external
decoupling is necessary, and the reference voltages are
not available externally. This simplifies usage of the ADC
since two extremely sensitive pins, otherwise needed, are
removed from the interface.
The SLP_N signal can be used to set the full chip in Sleep
Mode. In this mode internal clocking is disabled, but some
low bandwidth circuitry is kept on to allow for a short
startup time. However, Sleep Mode represents a signifi-
cant reduction in supply current, and it can be used to
save power even for short idle periods.
Operational Modes
The operational modes are controlled with the PD_N and
SLP_N pins. If PD_N is set low, all other control pins are
overridden and the chip is set in Power Down mode. In
this mode all circuitry is completely turned off and the in-
ternal clock is disabled. Hence, only leakage current con-
The input clock should be kept running in all idle modes.
However, even lower power dissipation is possible in Power
Down mode if the input clock is stopped. In this case it is
important to start the input clock prior to enabling active mode.
Mechanical Dimensions
QFN-40 Package
D
Inches
Typ
–
0.0004
0.023
0.008 REF
0.010
Millimeters
Typ
–
0.01
0.65
0.2 REF
0.25
Symbol
A
Min
–
0.001
–
Max
0.035
0.002
0.028
Min
–
0.00
–
Max
0.9
D2
A
1
A
2
A
3
0.05
0.7
Pin 1 ID - Dia. 0.5
(Top Side)
1.14
F
Pin 1 ID - Dia. R
A
b
0.008
0.013
0.2
0.32
G
D
0.236 BSC
0.226 BSC
0.162
0.016
0.020 BSC
–
6.00 BSC
5.75 BSC
4.10
0.4
0.50 BSC
–
–
0.42
0.2
D
1
A3
A1
D
0.156
0.012
0.167
0.020
3.95
0.3
4.25
0.5
2
L
e
0.45
Pin 0 Exposed Pad
θ
1
0°
12°
–
0.024
–
0°
0.2
0.24
0.1
12°
–
0.6
–
F
G
R
0.008
0.0096
0.004
–
0.0168
0.008
NOTE:
Package dimensions in millimeter unless otherwise noted.
D
D2
D1
θ1
L
e
b
A2
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
Amplify the Human Experience
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
designed by
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
