ADVANCE Data Sheet
The quality of the input clock is extremely important for The voltage on the OVDD pin set the levels of the CMOS
high-speed, high-resolution ADCs. The contribution to SNR
from clock jitter with a full scale signal at a given frequency
is shown in the equation below:
outputs. The output drivers are dimensioned to drive a
wide range of loads for OVDD above 2.25V, but it is rec-
ommended to minimize the load to ensure as low transient
switching currents and resulting noise as possible. In ap-
plications with a large fanout or large capacitive loads, it
is recommended to add external buffers located close to
the ADC chip.
•
•
•
•
SNR
= 20 log (2 π F εt)
jitter
IN
where F is the signal frequency, and εt is the total rms
IN
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CK_EXT always
should be lower than the load on data outputs to ensure
sufficient timing margins.
For applications where jitter may limit the obtainable per-
formance, it is of utmost importance to limit the clock
jitter. This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specifications) and make sure the clock distribution is
well controlled. It might be advantageous to use analog
power and ground planes to ensure low noise on the sup-
plies to all circuitry in the clock distribution. It is of utmost
importance to avoid crosstalk between the ADC output bits
and the clock and between the analog input signal and
the clock since such crosstalk often results in harmonic
distortion.
The digital outputs can be set in tristate mode by setting
the OE_N signal high.
The CDK1308 employs digital offset correction. This means
that the output code will be 4096 with shorted inputs.
However, small mismatches in parasitics at the input
can cause this to alter slightly. The offset correction also
results in possible loss of codes at the edges of the full
scale range. With no offset correction, the ADC would clip
in one end before the other, in practice resulting in code
loss at the opposite end. With the output being centered
digitally, the output will clip, and the out of range flags will
be set, before max code is reached. When out of range
flags are set, the code is forced to all ones for over-range
and all zeros for under-range.
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter per-
formance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
If the clock is generated by other circuitry, it should be re-
timed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
Data Format Selection
The output data are presented on offset binary form
when DFRMT is low (connect to OV ). Setting DFRMT
SS
Digital Outputs
high (connect to OV ) results in 2’s complement output
DD
format. Details are shown in Table 1 below.
Digital output data are presented on parallel CMOS form.
Table 1: Data Format Description for 2V Full Scale Range
pp
Output data: D_9 : D_0
(DFRMT = 0, offset binary)
Output Data: D_9 : D_0
(DFRMT = 1, 2’s complement)
Differential Input Voltage (IP - IN)
1.0 V
+0.24mV
-0.24mV
-1.0V
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
01 1111 1111
00 0000 0000
11 1111 1111
10 0000 0000
©2008 CADEKA Microcircuits LLC
www.cadeka.com
13
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