欢迎访问ic37.com |
会员登录 免费注册
发布采购

CDK1307AILP40 参数 Datasheet PDF下载

CDK1307AILP40图片预览
型号: CDK1307AILP40
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 20/40/ 65 / 80MSPS , 12月13日位模拟至数字转换器(ADC ) [Ultra Low Power, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters (ADCs)]
分类和应用: 转换器
文件页数/大小: 15 页 / 1149 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
 浏览型号CDK1307AILP40的Datasheet PDF文件第7页浏览型号CDK1307AILP40的Datasheet PDF文件第8页浏览型号CDK1307AILP40的Datasheet PDF文件第9页浏览型号CDK1307AILP40的Datasheet PDF文件第10页浏览型号CDK1307AILP40的Datasheet PDF文件第11页浏览型号CDK1307AILP40的Datasheet PDF文件第12页浏览型号CDK1307AILP40的Datasheet PDF文件第13页浏览型号CDK1307AILP40的Datasheet PDF文件第15页  
ADVANCE Data Sheet  
Table 1: Data Format Description for 2V Full Scale Range  
pp  
Output data: D_12 : D_0  
Output Data: D_12 : D_0  
(DFRMT = 1, 2’s complement)  
Differential Input Voltage (IP - IN)  
(DFRMT = 0, offset binary)  
1 1111 1111 1111  
1 0000 0000 0000  
0 1111 1111 1111  
0 0000 0000 0000  
1.0 V  
+0.24mV  
-0.24mV  
-1.0V  
0 1111 1111 1111  
0 0000 0000 0000  
1 1111 1111 1111  
1 0000 0000 0000  
Reference Voltages  
Operational Modes  
The operational modes are controlled with the PD_N and  
SLP_N pins. If PD_N is set low, all other control pins are  
overridden and the chip is set in Power Down mode. In  
this mode all circuitry is completely turned off and the  
internal clock is disabled. Hence, only leakage current  
contributes to the Power Down Dissipation. The startup  
time from this mode is longer than for other idle modes  
as all references need to settle to their final values before  
normal operation can resume.  
The reference voltages are internally generated and buff-  
ered based on a bandgap voltage reference. No external  
decoupling is necessary, and the reference voltages are  
not available externally. This simplifies usage of the ADC  
since two extremely sensitive pins, otherwise needed, are  
removed from the interface.  
If a lower full scale range is required the 13-bit output  
word provides sufficient resolution to perform digital scaling  
with an equivalent impact on noise compared to adjusting  
the reference voltages.  
The SLP_N bus can be used to power down each channel  
independently, or to set the full chip in Sleep Mode. In this  
mode internal clocking is disabled, but some low band-  
width circuitry is kept on to allow for a short startup time.  
However, Sleep Mode represents a significant reduction in  
supply current, and it can be used to save power even for  
short idle periods.  
A simple way to obtain 1.0V input range with a 12-bit  
pp  
output word is shown in the Table 2 below. Note that only  
2‘s complement output data are available in this mode  
and that out of range conditions must be determined  
based on a two bit output. The output code will wrap  
around when the code goes outside the full scale range.  
The out of range bits should be used to clamp the output  
data for overrange conditions.  
The input clock could be kept running in all idle modes.  
However, even lower power dissipation is possible in  
Power Down mode if the input clock is stopped. In this  
case it is important to start the input clock prior to en-  
abling active mode.  
Table 2: Data Format Description for 1V Full Scale Range  
pp  
Differential Input  
Voltage  
Output data: D_11:  
D_0 (DFRMT = 0)  
(2’s Complement)  
Output Data: D_11:  
Out of Range  
Out of Range  
(Use Logical AND Function for &)  
D_0 (DFRMT = 1)  
(Use Logical AND Function for &)  
(IP - IN)  
(2’s Complement)  
0111 1111 1111  
0111 1111 1111  
0000 0000 0000  
1111 1111 1111  
1000 0000 0000  
1000 0000 0000  
> 0.5V  
0.5V  
0111 1111 1111  
0111 1111 1111  
0000 0000 0000  
1111 1111 1111  
1000 0000 0000  
1000 0000 0000  
D_12 = 1 & D_11 = 1  
D_12 = 0 & D_11 = 1  
+0.24mV  
-0.24mV  
-0.5V  
< -0.5V  
D_12 = 0 & D_11 = 0  
D_12 = 1 & D_11 = 0  
©2008 CADEKA Microcircuits LLC  
www.cadeka.com  
14