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CDK1307AILP40 参数 Datasheet PDF下载

CDK1307AILP40图片预览
型号: CDK1307AILP40
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 20/40/ 65 / 80MSPS , 12月13日位模拟至数字转换器(ADC ) [Ultra Low Power, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters (ADCs)]
分类和应用: 转换器
文件页数/大小: 15 页 / 1149 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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ADVANCE Data Sheet  
a recommended configuration using a transformer. Make  
sure that a transformer with sufficient linearity is selected,  
and that the bandwidth of the transformer is appropriate.  
The bandwidth should exceed the sampling rate of the  
ADC with at least a factor of 10. It is also important to  
keep phase mismatch between the differential ADC inputs  
small for good HD2 performance. This type of transformer  
coupled input is the preferred configuration for high fre-  
quency signals as most differential amplifiers do not have  
adequate performance at high frequencies. If the input  
signal is traveling a long physical distance from the signal  
source to the transformer (for example a long cable), kick-  
backs from the ADC will also travel along this distance. If  
these kick-backs are not terminated properly at the source  
side, they are reflected and will add to the input signal at  
the ADC input. This could reduce the ADC performance.  
To avoid this effect, the source must effectively terminate  
the ADC kick-backs, or the traveling distance should be  
very short. If this problem could not be avoided, the cir-  
cuit in Figure 6 can be used.  
Note that startup time from Sleep Mode and Power Down  
Mode will be affected by this filter as the time required  
to charge the series capacitors is dependent on the filter  
cut-off frequency.  
If the input signal has a long traveling distance, and the  
kick-backs from the ADC not are effectively terminated at  
thesignalsource,theinputnetworkofFigure6canbeused.  
The configuration is designed to attenuate the kickback  
from the ADC and to provide an input impedance that looks  
as resistive as possible for frequencies below Nyquist.  
Values of the series inductor will however depend on board  
design and conversion rate. In some instances a shunt ca-  
pacitor in parallel with the termination resistor (e.g. 33pF)  
may improve ADC performance further. This capacitor at-  
tenuate the ADC kick-back even more, and minimize the  
kicks traveling towards the source. However, the imped-  
ance match seen into the transformer becomes worse.  
33Ω  
220Ω  
33Ω  
120nH  
1:1  
33Ω  
R
T
RT  
47Ω  
pF  
68Ω  
optional  
120nH  
33Ω  
Figure 4. Transformer-Coupled Input  
Figure 6. Alternative Input Network  
Figure 5 shows AC-coupling using capacitors. Resistors  
from the CM_EXT output, R , should be used to bias the  
differential input signals to the correct voltage. The series  
CM  
Clock Input And Jitter Considerations  
Typically high-speed ADCs use both clock edges to gener-  
ate internal timing signals. In the CDK1307 only the rising  
edge of the clock is used. Hence, input clock duty cycles  
between 20% and 80% is acceptable.  
capacitor, C , form the high-pass pole with these resistors,  
I
and the values must therefore be determined based on  
the requirement to the high-pass cut-off frequency.  
The input clock can be supplied in a variety of formats.  
The clock pins are AC-coupled internally, and hence a wide  
common mode voltage range is accepted. Differential  
clock sources as LVDS, LVPECL or differential sine wave  
can be connected directly to the input pins. For CMOS  
inputs, the CLKN pin should be connected to ground, and  
the CMOS clock signal should be connected to CLKP. For  
differential sine wave clock input the amplitude must be  
Ω
pF  
Ω
Figure 5. AC-Coupled Input  
at least ±800mV .  
pp  
©2008 CADEKA Microcircuits LLC  
www.cadeka.com  
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