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CDK1306CSO28 参数 Datasheet PDF下载

CDK1306CSO28图片预览
型号: CDK1306CSO28
PDF下载: 下载PDF文件 查看货源
内容描述: 10位, 40 MSPS 160MW A / D转换器 [10-bit, 40 MSPS 160mW A/D Converter]
分类和应用: 转换器
文件页数/大小: 11 页 / 1296 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet
a specific case. V
REF
of 4.0V is applied to V
RHF
, and V
RLF
is tied to AGND. A 90mV drop is seen at V
RHS
(= 3.91V),
and a 75mV increase is seen at V
RLS
(= 0.075V).
Analog Input
V
IN
is the analog input. The input voltage range is from
V
RLS
to V
RHS
(typically 4.0V) and will scale proportionally
with respect to the voltage reference. (See Voltage Refer-
ence section.)
The drive requirements for the analog inputs are very
minimal when compared to most other converters due to
the CDK1306 extremely low input capacitance of only 5pF
and very high input resistance of 50kΩ.
The analog input should be protected through a series
resistor and diode clamping circuit as shown in Figure 6.
CDK1306
10-bit, 40 MSPS 160mW A/D Converter
Figure 4. Ladder Force/Sense Circuit
REV 1A
Figure 6. Recommended Input Protection Circuit
Calibration
The CDK1306 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and
offset errors are continually adjusted to 10-bit accuracy
during device operation. This process is completely trans-
parent to the user.
Upon powerup, the CDK1306 begins its calibration
algorithm. In order to achieve the calibration accuracy
required, the offset and gain adjustment step size is a
fraction of a 10-bit LSB. Since the calibration algorithm
is an oversampling process, a minimum of 10,000 clock
cycles are required. This results in a minimum calibration
time upon powerup of 250μs (for a 40MHz clock). Once
calibrated, the CDK1306 remains calibrated over time and
temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for
the CDK1306 to remain in calibration.
9
Figure 5. Reference Ladder Circuit
Typically, the top side voltage drop for V
RHF
to V
RHS
will
equal:
V
RHF
– V
RHS
= 2.25 % of (V
RHF
– V
RLF
) (typical)
and the bottom side voltage drop for V
RLS
to V
RLF
will
equal:
V
RLS
– V
RLF
= 1.9 % of (V
RHF
– V
RLF
) (typical)
Figure 5 shows an example of expected voltage drops for
©2008 CADEKA Microcircuits LLC
www.cadeka.com