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(TIF bit in Timer Control Register, TCR) is set. Once timer interrupt flag is set, an interrupt is generated to the
CPU only if the TIM bit in the TCR and 1-bit in the CCR are cleared. When an interrupt is recognized, after
completion of the current instruction, the processor proceeds to store the appropriate registers on the stack and
then fetches the timer interrupt vector from locations $1FF6 and $1FF7. See Section 6.7.2 for details on the
timer interrupts.
The counter may be read at any time by the processor without disturbing the count. The contents of the
counter become stable prior to the read portion of a cycle and do not change during the read. The timer interrupt
flag remains set until cleared by the software. If a write occurs before the timer interrupt is served, the interrupt
is lost. The timer interrupt flag may also be sued as a scanned status bit in a non-interrupt mode of operation.
The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit
0,1,2(PR0,PR1,PR2) of TCR are programmed to choose the appropriate prescaler output which is used as the
8-bit counter clock input. The processor cannot write into or read from the prescaler; however, its contents can
be cleared to all zeros by writing to the PRER bit in the TCR. This will allow for truncation-free counting.
TDR
CK
8
SYSTEM
CLOCK
PRESCALER
PRESCALER
RESET
8
PRESCALER SELECT LOGIC
OVERFLOW
INTERRUPT
CONTROL
TCR
PRER PR2 PR1 PR0
8
TIF TIM
Figure 6.5.1
6.6 Remote Control Carrier Synthesizer
The device has a built carrier synthesizer for infrared or RF remote control circuits. The carrier’s duty is
1/3. The carrier synthesizer can be programmed in several different prescaler ratios by setting FC[2:0] of OTP’s
OPTION BIT. IROUT of the remote control carrier synthesizer output is shown in Figure 6.6.1.
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