Data Sheet
2W STEREO AUDIO POWER AMPLIFIER WITH SHUTDOWN
AA4003
Application Information (Continued)
2
2VDD
2×52
P
=
=
=1.266W
DBTLMAX
π 2RL 3.142 ×4
Power Dissipation, Efficiency and Thermal
Design Consideration
For Class AB amplifiers, Formula 4 is the basic
equation of efficiency worked in BTL configuration,
per channel, total power dissipation P
=2*
DTOTAL
P
=2.53W. According to formula 6, maximum
DBTLMAX
ambient temperature is,
πVP
.......................................................(4)
η =
=150-50*2.53=23.5 oC
4VDD
TA = TJMAX −θJA ∗ P
DBTLMAX
here V is output peak voltage across the load.
That is to say, if user wants AA4003 to delivery 2W
P
power per channel to 4Ω load at V =5.0V, BTL
DD
Thermal dissipation becomes major concern when
delivering more output power especially in BTL mode.
The maximum power dissipation can be calculated by
following equation.
mode, ambient temperature has to hold lower than
23.5oC. When junction temperature exceeds about
170oC, OTSD feature will be enabled, and shutdown
the device to limit total power dissipation.
TJMAX −TA
......................................(5)
There is an exposed thermal pad on bottom of the chip
to provide the direct thermal path from die to heat sink.
It is recommended to use copper on the surface of
Printed Circuit Board as heat sink. To dig some matrix
regular holes under chip, remove mask of this area
PDMAX
=
θJA
Here
T
is maximum operating junction
JMAX
temperature, 150oC, T is ambient temperature, θ is
A
JA
thermal resistance from junction to ambient, which is copper, and make sure to keep them contact well when
50oC/W for TSSOP-20 (EDP), given in datasheet.
soldering on PCB are also recommended. (See Figure
21)
Assuming T is 25oC, the maximum power dissipation
A
P
is about 2.5W according to formula 6.
DMAX
Recommended PCB Layout for AA4003
Using wide traces for power supply to reduce power
losses caused by parasitic resistance in all outputs is
useful to help releasing heat away from the chip. It is
recommended to place bypass capacitor, power supply
bypass capacitors as close as possible to the chip.
Figure 21 and Figure 22 show the recommended layout
for double layer PCB.
There is an other formula about power dissipation
which is determined by supply voltage and load
resistance.
2
2VDD
PDBTLMAX
=
......................................(6)
π 2RL
If power dissipation calculated in an application is
larger than that package permitted, there will be a need
to assemble an additional heat sink, or keep ambient
temperature around the chip low, or increase load
resistance, or decrease power supply voltage.
Here is an example. Assuming V =5.0V, R =4Ω,
DD
L
stereo in BTL mode,
Oct. 2007 Rev. 1. 1
BCD Semiconductor Manufacturing Limited
13
BCDSEMI [ BCD SEMICONDUCTOR MANUFACTURING LIMITED ]
