PCM1800
SBAS071B–OCTOBER 2000–REVISED AUGUST 2008 ............................................................................................................................................... www.ti.com
THEORY OF OPERATION
The PCM1800 consists of a band-gap reference, two channels of a single-to-differential converter, a fully
differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface
circuit. The block diagram illustrates the total architecture of the PCM1800 and the analog front-end diagram
illustrates the architecture of the single-to-differential converter and the antialiasing filter. Figure 18 illustrates the
architecture of the 5th-order delta-sigma modulator and transfer functions.
An internal high-precision reference with two external capacitors provides all the reference voltages that are
required by the converter, and defines the full-scale voltage range of both channels. The internal
single-to-differential voltage converter saves the design, space, and extra parts needed for external circuitry
required by many delta-sigma converters. The internal full-differential architecture provides a wide dynamic range
and excellent power-supply rejection performance.
The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and
simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators
which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a 1-bit DAC. The
delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain.
The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels.
The 64-fS, 1-bit stream from the modulator is converted to 1-fS, 20-bit digital data by the decimation filter, which
also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a
high-pass filter, and the filtered output is converted to time-multiplexed serial signals through a serial interface
which provides flexible serial formats and master/slave modes.
Analog
In
−
−
st
nd
rd
th
th
1
2
3
4
5
X(z)
+
+
+
SW-CAP
SW-CAP
SW-CAP
SW-CAP
SW-CAP
Qn(z)
Integrator
Integrator
Integrator
Integrator
Integrator
−
Digital
Out
Y(z)
+
+
+
+
+
+
+
+
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
B0005-01
Figure 18. Simplified Diagram of the PCM1800 5th-Order Delta-Sigma Modulator
SYSTEM CLOCK
The system clock for the PCM1800 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling
frequency. The system clock must be supplied on SYSCLK (pin 16).
The PCM1800 also has a system-clock detection circuit which automatically senses if the system clock is
operating at 256 fS, 384 fS, or 512 fS.
When the 384-fS or 512-fS system clock is in slave mode, the system clock is divided into 256 fS automatically.
The 256-fS clock is used to operate the digital filter and the modulator. Table 1 lists the relationship of typical
sampling frequencies and system clock frequencies. Figure 19 illustrates the system clock timing.
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