Load (Output Device) Characteristics
•
Use devices with very low bias current.
Generally, FET
input amplifiers should be used for low-level signals less
than 50mV FSR. Low bias current bipolar input amplifi-
ers are acceptable for signal ranges higher than 50mV
FSR. Bias current matching will determine the input
offset.
• The system dc common-mode rejection (CMR) can never
be better than the combined CMR of the multiplexer and
driven load. System CMR will be less than the device
which has the lower CMR figure.
• Load impedances, differential and common-mode, should
be 10
10
Ω
or higher.
SOURCE CHARACTERISTICS
• The source impedance unbalance will produce offset,
common-mode and channel-to-channel gain-scatter er-
rors. Use sources which do not have large impedance
unbalances if at all possible.
• Keep source impedances as low as possible to minimize
resistive loading errors.
• Minimize ground loops. If signal lines are shielded,
ground all shields to a common point at the system analog
common.
If the MPC507A is used for multiplexing high-level signals
of 1V to 10V full-scale ranges, the foregoing precautions
should still be taken, but the parameters are not as critical as
for low-level signal applications.
DYNAMIC CHARACTERISTICS
Settling Time
The gate-to-source and gate-to-drain capacitance of the
CMOS FET switches, the RC time constants of the source
and the load determine the settling time of the multiplexer.
Governed by the charge transfer relation i = C (dV/dt), the
charge currents transferred to both load and source by the
analog switches are determined by the amplitude and rise
time of the signal driving the CMOS FET switches and the
gate-to-drain and gate-to-source junction capacitances as
shown in Figures 3 and 4. Using this relationship, one can
see that the amplitude of the switching transients seen at the
source and load decrease proportionally as the capacitance
of the load and source increase. The trade-off for reduced
switching transient amplitude is increased settling time. In
effect, the amplitude of the transients seen at the source and
load are:
dV
L
= (i/C) dt
where i = C (dV/dt) of the CMOS FET switches
C = load or source capacitance
The source must then redistribute this charge, and the effect
of source resistance on settling time is shown in the Typical
Performance Curves. This graph shows the settling time for
a 20V step change on the input. The settling time for smaller
step changes on the input will be less than that shown in the
curve.
R
SA
Node A
C
SA
Source
C
SB
Rd
A
Cd
A
Z
CM
R
CMS
MPC507A Load
Channel
Rd
B
Node B
Cd
B
C
CMS
R
SB
FIGURE 4. Settling and Common-Mode Effects—
MPC507A
Switching Time
This is the time required for the CMOS FET to turn ON
after a new digital code has been applied to the Channel
Address inputs. It is measured from the 50 percent point of
the address input signal to the 90 percent point of the analog
signal seen at the output for a 10V signal change between
channels.
Crosstalk
Crosstalk is the amount of signal feedthrough from the
seven (MPC507A) or 15 (MPC506A) OFF channels ap-
pearing at the multiplexer output. Crosstalk is caused by the
voltage divider effect of the OFF channel, OFF resistance
and junction capacitances in series with the R
ON
and R
S
impedances of the ON channel. Crosstalk is measured with
a 20Vp-p 1000Hz sine wave applied to all off channels. The
crosstalk for these multiplexers is shown in the Typical
Performance Curves.
MPC506A Channel
Source
Load
Node A
R
S
C
S
C
L
R
L
FIGURE 3. Settling Time Effects—MPC506A.
6
MPC506A, MPC507A
www.ti.com
SBFS018A
BURR-BROWN [ BURR-BROWN CORPORATION ]
