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MPC506AU/1K 参数 Datasheet PDF下载

MPC506AU/1K图片预览
型号: MPC506AU/1K
PDF下载: 下载PDF文件 查看货源
内容描述: 单端16通道/差分8通道CMOS模拟多路复用器 [Single-Ended 16-Channel/Differential 8-Channel CMOS ANALOG MULTIPLEXERS]
分类和应用: 复用器光电二极管
文件页数/大小: 15 页 / 419 K
品牌: BURR-BROWN [ BURR-BROWN CORPORATION ]
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DISCUSSION OF
SPECIFICATIONS
DC CHARACTERISTICS
The static or dc transfer accuracy of transmitting the multi-
plexer input voltage to the output depends on the channel
ON resistance (R
ON
), the load impedance, the source imped-
ance, the load bias current and the multiplexer leakage
current.
Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
Source resistance loading error
Multiplexer ON resistance error
dc offset error caused by both load bias current and
multiplexer leakage current.
Resistive Loading Errors
The source and load impedances will determine the input
resistive loading errors. To minimize these errors:
Keep loading impedance as high as possible.
This mini-
mizes the resistive loading effects of the source resistance
and multiplexer ON resistance. As a guideline, load
impedance of 10
8
or greater will keep resistive loading
errors to 0.002% or less for 1000Ω source impedances. A
10
6
load impedance will increase source loading error
to 0.2% or more.
Use sources with impedances as low as possible.
A
1000Ω source resistance will present less than 0.001%
loading error and 10kΩ source resistance will increase
source loading error to 0.01% with a 10
8
load impedance.
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1).
I
BIAS
V
M
V
S1
R
S16
R
OFF
I
L
Measured
Voltage
Z
L
V
S16
Input Offset Voltage
Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20µV if a 1kΩ source is used. In general,
for the MPC506A, the OFFSET voltage at the output is
determined by:
V
OFFSET
= (I
B
+ I
L
) (R
ON
+ R
S
)
where I
B
= Bias current of device multiplexer is driving
I
L
= Multiplexer leakage current
R
ON
= Multiplexer ON resistance
R
S
= Source resistance
Differential Multiplexer Static Accuracy
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current
mismatch, load differential impedance mismatch, and com-
mon-mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
Referring to Figure 2, the effects of these errors can be
minimized by following the general guidelines described in
this section, especially for low-level multiplexing applica-
tions.
R
S1
R
ON
R
S1A
R
ON1A
I
BIAS A
Cd/2
R
CM
I
L
V
S1
R
S1B
R
ON1B
I
BIAS B
Cd/2
Rd/2
R
S8A
R
OFF8A
Rd/2
R
CM
Z
L
C
CM
R
CM1
FIGURE 1. MPC506A Static Accuracy Equivalent Circuit.
V
S8
Source and Multiplexer Resistive Loading Error
(R
S
+
R
ON
)
=
R
S
+
R
ON
×
100
R
S
+
R
ON
+
R
L
R
CM8
R
S8B
R
OFF8B
where R
S
= source resistance
R
L
= load resistance
R
ON
= multiplexer ON resistance
FIGURE 2. MPC507A Static Accuracy Equivalent Circuit.
MPC506A, MPC507A
SBFS018A
www.ti.com
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