tLD
tWCS
CS
tWS
tWH
R/W
tRCS
tAH
tAS
CS
A0/A1
tRDH
tRDS
tLWD
R/W
tAS
tAH
LDAC
±0.012% of FSR
Error Band
tDH
tDS
A0/A1
Data In
tDZ
tS
Data Out
Data Valid
tCSD
VOUT
Data Read Timing
Data Write Timing
±0.012% of FSR
Error Band
tRESET
RESET
tS
+FS
VOUT, DAC7725
–FS
±0.012% of FSR
Error Band
+FS
VOUT, DAC7724
–FS
Mid-Scale
±0.012% of FSR
DAC7724/25 Reset Timing
Error Band
FIGURE 4. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
MIN
TYP
MAX
UNITS
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tAS
tAH
tLD
tDS
tDH
tLWD
tRESET
tS
200
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
100
100
160
50
0
0
0
0
10
0
0
50
50
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
LDAC Delay from CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
RESET LOW Time
Settling Time
10
TABLE II. Timing Specifications (TA = –40°C to +85°C).
®
15
DAC7724, 7725
BB [ BURR-BROWN CORPORATION ]
