DAC7634
www.ti.com
SBAS134A–JULY 2004–REVISED AUGUST 2004
RF
VOUT Sense
VOUT
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
VREF
VREFH Sense
VREF
VREFL Sense
H
L
Figure 48. DAC7634 Architecture
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
VOUTA Sense
VOUT
0V to +2.5V
NC
A
3
Serial Data In
Clock
SDI
AGND
VSS
4
DGND
CLK
5
VREFLAB Sense
VREFLAB
6
DGND
LDAC
DGND
LOAD
DGND
CS
+2.5000V
7
VREFH AB
Load DAC Registers
Load
8
VREFH AB Sense
VOUTB Sense
9
0V to +2.5V
0V to +2.5V
+2.5000V
10
11
12
13
VOUT
OUTC Sense
VOUT
B
V
Chips Select
Serial Data Out
DGND
SDO
DAC7634
C
VREFH CD Sense
VREFH CD
14 DGND
15
16
RSTSEL
DGND
VREFL CD
VREFL CD Sense
VOUTD Sense
Reset DAC Registers
17 RST
0V to +2.5V
18
19
DGND
NC
VOUTD
VSS
VSS
20 NC
21
22
23
24
DGND
DGND
VDD
AGND
AGND
VCC
0.1
F
1
VDD
VCC
+5V
NC = No Connection
Figure 49. Basic Single-Supply Operation of the DAC7634
17
BB [ BURR-BROWN CORPORATION ]
