received in the first 16 bits of each baud period. The
remaining 32-bit periods are not used for Data In. Data Out
is transmitted during the first 16 bits of the baud period. A
second interpolated value is transmitted in subsequent bits of
the baud period.
be valid on the rising edge of the tx48xCLK. The AFE1124
reads Data In on the rising edge of the tx48xCLK. The bits
are defined in Table I. Data In is read by the AFE1124
during the first 16 bits periods of each baud period. Only the
first 8 bits are used in the AFE1124. The second 8 bits are
reserved for use in the future products. The remaining 32
bits periods of the baud period are not used for Data In.
txbaudCLK: The transmit data baud rate, generated by the
DSP. It is 392kHz for T1 or 584kHz for E1. It may vary from
32kHz (64kbps) to 584kHz (1.168Mbps).
Data In Bits:
tx48xCLK: The transmit pulse former oversampling sam-
pling clock, generated by the DSP. It is 48x the transmit
symbol rate or 28.032MHz for 584kHz symbol rate. This
clock should run continuously.
tx enable signal—This bit controls the tx Symbol definition
bits. If this bit is 0, only a 0 symbol is transmitted regardless
of the state of the tx Symbol definition bits. If this bit is 1,
the tx Symbol definition bits determine the output symbol.
Data In: This is a 16-bit output data word sent from the DSP
to the AFE. The sixteen bits include tx symbol information
and other control bits, as described below. The data should
be clocked out of the DSP on the falling edge and it should
tx Symbol Definition—These two bits determine the output
2B1Q symbol transmitted.
Rx Gain Settings—These bits set the gain of the receive
channel programmable gain amplifier.
MSB
LSB
1
2
3
1
1
8
Reserved
tx Boost
Loopback
rx Gain
tx Symbol
tx Enable
FIGURE 3. Data In Word.
4ns
4ns
rxbaudCLK
A
B
from DSP
4ns
4ns
14
rx48xCLK
from DSP
48
1
15
16
17
23
24
25
26
39
40
47
48
1
Data Out
from AFE1124
MSB
Bit 15
LSB
Bit 0
MSB
Bit 15
LSB
Bit 0
MSB
Bit 15
trx1
Data 1
Interdata 8 Bits
Interdata 8 Bits
Data 1a
Data 2
Receive Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the rxbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the
rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB of
Data 1, the AFE1124 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of
rx48xCLK until Data Out is stable is trx1
.
MIN
9ns
MAX
14ns
trx1
(4) The AFE1124 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is
synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time
from the falling edge of rxbaud CLK until the MSB of Data 1 is stable is trx1
.
FIGURE 4. Receive Timing Diagram.
®
7
AFE1124
BB [ BURR-BROWN CORPORATION ]
