SNR is given by the following equation. If this value is near
your system requirements, input clock jitter must be reduced.
Jitter SNR
=
20 log
1
rms signal to rms noise
2
π
ƒ
IN
t
A
where: ƒ
IN
is input signal frequency
t
A
is rms clock jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have 50% duty cycle (t
H
= t
L
), along with fast rise and fall
times of 2ns or less. To estimate the typical performance
deviation for clock duty cycles in the range of 50%
±7.5%,
refer to Figure 9. The clock input of the ADS826 can be
driven with either 3V or 5V logic levels. Using low-voltage
logic (3V) may lead to improved AC performance of the
converters.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS823 and ADS826 and affect
performance. If necessary, external buffers or latches close
to the converter’s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS823 and ADS826 from any digital noise
activities on the bus coupling back high frequency noise.
Digital Output Driver (VDRV)
The ADS823 and ADS826 feature a dedicated supply pin for
the output logic drivers, VDRV, which is not internally
connected to the other supply pins. Setting the voltage at
VDRV to +5V or +3V, the ADS823 and ADS826 produce
corresponding logic levels and can directly interface to the
selected logic family. The output stages are designed to
supply sufficient current to drive a variety of logic families.
However, it is recommended to use the ADS823 and ADS826
with +3V logic supply. This will lower the power dissipation
in the output stages due to the lower output swing and reduce
current glitches on the supply line which may affect the AC-
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
SINGLE-ENDED INPUT
(IN = CMV)
+FS –1LSB (IN = REFT)
+1/2 Full Scale
Bipolar Zero (IN = V
CM
)
–1/2 Full Scale
–FS (IN = REFB)
STRAIGHT OFFSET BINARY
(SOB)
1111111111
1100000000
1000000000
0100000000
0000000000
80
75
70
SFDR
(dBFS)
65
SNR
60
55
50
57.5
55
52.5
50
47.5
45
42.5
Clock Duty Cycle (t
H
/t
L
x 100%)
TABLE I. Coding Table for Single-Ended Input Configura-
tion with IN tied to the Common-Mode Voltage
(V
CM
).
STRAIGHT OFFSET BINARY
(SOB)
1111111111
1100000000
1000000000
0100000000
0000000000
DIFFERENTIAL INPUT
FIGURE 9. ADS823 and ADS826 Duty Cycle Sensitivity.
Digital Outputs
The output data format of the ADS823 and ADS826 is in
positive Straight Offset Binary code (see Tables I and II). This
format can easily be converted into the Two’s Binary Comple-
ment code by inverting the MSB.
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full Scale
Bipolar Zero (IN = IN = V
CM
)
–1/2 Full Scale
–FS (IN = +2V, IN = +3V)
TABLE II. Coding Table for Differential Input Configura-
tion and 2Vp-p Full-Scale Range.
®
ADS823, ADS826
12
BURR-BROWN [ BURR-BROWN CORPORATION ]
