the resistive reference ladder. The bandgap reference circuit
includes logic functions that allow to set the analog input
swing of the ADS823 and ADS826 to either a 1Vp-p or
2Vp-p full-scale range simply by tying the RSEL pin to a
Low or High potential, respectively. While operating the
ADS823 and ADS826 in the external reference mode, the
buffer amplifiers for the REFT and REFB are disconnected
from the reference ladder.
As shown, the ADS823 and ADS826 have internal 50kΩ
pull-up resistors at the range select pin (RSEL) and refer-
ence select pin (INT/EXT). Leaving those pins open config-
ures the ADS823 for a 2Vp-p input range and external
reference operation. Setting the ADS823 up for internal
reference mode requires bringing the INT/EXT pin Low.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. The resistor ladders
of the ADS823 and ADS826 are divided into several seg-
ments and have two additional nodes, ByT and ByB, which
are brought out for external bypassing only (Figure 6). To
ensure proper operation with any reference configurations, it
is necessary to provide solid bypassing at all reference pins
in order to keep the clock feedthrough to a minimum. All
bypassing capacitors should be located as close to their
respective pins as possible.
The common-mode voltage available at the CM pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a com-
mon-mode voltage is given in Figure 7. Here, two external
precision resistors (tolerance 1% or better) are located
between the top and bottom reference pins. The common-
mode voltage, V
CM
, will appear at the midpoint.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved tempera-
ture performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The external references can vary as long as the value of the
external top reference REFT
EXT
stays within the range of
(V
S
– 1.25V) and (REFB + 0.8V), and the external bottom
reference REFB
EXT
stays within 1.25V and (REFT – 0.8V),
see Figure 8.
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high-speed,
high-resolution A/D converters. Clock jitter leads to aperture
jitter (t
A
), which adds noise to the signal being converted. The
ADS823 and ADS826 samples the input signal on the rising
edge of the CLK input. Therefore, this edge should have the
lowest possible jitter. The jitter noise contribution to total
REFT
+3.5V
R
1
1.6kΩ
ADS823
ADS826
REFB
+1.5V
R
2
1.6kΩ
0.1µF
V
CM
+2.5V
0.1µF
FIGURE 7. Alternative Circuit to Generate CM Voltage.
+5V
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
+VS
V
IN
IN
ADS823
ADS826
V
CM
+2.5V
DC
IN
REFT
ByT
GND
ByB
REFB
INT/EXT
B
A
RSEL
GND
External Top Reference
REFT = REFB +0.8V to +3.75V
4 x 0.1µF || 2.2µF
External Bottom Reference
REFB = REFT –0.8V to +1.25V
FIGURE 8. Configuration Example for External Reference Operation.
11
®
ADS823, ADS826
BURR-BROWN [ BURR-BROWN CORPORATION ]
