THEORY OF OPERATION
The ADS802 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 12-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock that has a non-overlapping 2-
phase signal,
φ1
and
φ2.
At the sampling time, the input
signal is sampled on the bottom plates of the input capaci-
tors. In the next clock phase,
φ2,
the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between C
I
and C
H
, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has 11 stages with each
stage containing a 2-bit quantizer and a 2-bit Digital-to-
Analog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to time-
Op Amp
Bias
φ1
V
CM
φ1
C
H
C
I
IN
IN
φ1
φ1
φ2
C
I
C
H
φ1
Input Clock (50%)
Op Amp
Bias
Internal Non-Overlapping Clock
φ1
φ2
φ1
V
CM
φ1
φ1
φ2
OUT
OUT
φ2
FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
IN
IN
Input
T/H
2-Bit
Flash
STAGE 1
2-Bit
DAC
Digital Delay
Σ
x2
+
–
Digital Delay
B1 (MSB)
B2
Digital Error Correction
2-Bit
Flash
STAGE 2
2-Bit
DAC
B3
B4
B5
B6
B7
B8
B9
B10
Digital Delay
B11
B12 (LSB)
Σ
x2
+
–
2-Bit
Flash
STAGE 10
2-Bit
DAC
Σ
x2
+
–
STAGE 11
2-Bit
Flash
Digital Delay
FIGURE 2. Pipeline A/D Converter Architecture.
ADS802
SBAS039B
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