align it with the data created from the following quantizer
stages. This aligned data is fed into a digital error correction
circuit that can adjust the output data based on the informa-
tion found on the redundant bits. This technique gives the
ADS802 excellent differential linearity and ensures no miss-
ing codes at the 12-bit level.
DIGITAL OUTPUT DATA
The 12-bit output data is provided at CMOS logic levels. The
standard output coding is Straight Offset Binary (SOB) where
a full-scale input signal corresponds to all “1s” at the output,
as shown in Table I. This condition is met with pin 19 “LO” or
Floating due to an internal pull-down resistor. By applying a
logic “HI” voltage to this pin, a Binary Two’s Complement
(BTC) output will be provided where the most significant bit
is inverted. The digital outputs of the ADS802 can be set to
a high-impedance state by driving OE (pin 18) with a logic
“HI”. Normal operation is achieved with pin 18 “LO” or floating
due to internal pull-down resistors. This function is provided
for testability purposes and is not meant to drive digital buses
directly, or be dynamically changed during the conversion
process.
Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS802 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired.
The ADS802 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of
+1.25V to +3.25V. Since each input is 2Vp-p and 180° out-
of-phase with the other, a 4V differential input signal to the
quantizer results. As shown in Figure 3, the positive full-scale
reference (REFT) and the negative full-scale (REFB) are
brought out for external bypassing. In addition, the common-
mode voltage (CM) may be used as a reference to provide
the appropriate offset for the driving circuitry. However, care
must be taken not to appreciably load this reference node.
For more information regarding external references, single-
ended input, and ADS802 drive circuits, refer to the applica-
tions section.
OUTPUT CODE
SOB
PIN 19
FLOATING or LOW
BTC
PIN 19
HIGH
DIFFERENTIAL INPUT(1)
+FS (IN = +3.25V, IN = +1.25V)
+FS – 1LSB
+FS – 2LSB
+3/4 Full-Scale
+1/2 Full-Scale
+1/4 Full-Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full-Scale
111111111111
111111111111
111111111110
111000000000
110000000000
101000000000
100000000001
100000000000
011111111111
011000000000
010000000000
001000000000
000000000001
000000000000
011111111111
011111111111
011111111110
011000000000
010000000000
001000000000
000000000001
000000000000
111111111111
111000000000
110000000000
101000000000
100000000001
100000000000
–1/2 Full-Scale
–3/4 Full-Scale
–FS + 1LSB
–FS (IN = +1.25V, IN = +3.25V)
NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS802.
ADS802
+3.25V
APPLICATIONS
REFT
23
DRIVING THE ADS802
0.1µF
2kΩ
The ADS802 has a differential input with a common-mode of
+2.25V. For AC-coupled applications, the simplest way to
create this differential input is to drive the primary winding of
a transformer with a single-ended input. A differential output is
created on the secondary if the center tap is tied to the
common-mode voltage of +2.25V, as in Figure 4. This trans-
To
Internal
Comparators
CM
22
21
+2.25V
2kΩ
REFB
0.1µF
+1.25V
FIGURE 3. Internal Reference Structure.
22 CM
0.1µF
CLOCK REQUIREMENTS
26
IN
IN
The CLK pin accepts a CMOS level clock input. The rising
and falling edges of the externally applied convert command
clock controls the various interstage conversions in the
pipeline. Therefore, the duty cycle of the clock should be held
at 50% with low jitter and fast rise-and-fall times of 2ns or
less. This is particularly important when digitizing a high-
frequency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten some
of the interstage settling times, thus degrading the SNR and
DNL performance.
ac Input
Signal
ADS802
22pF
27
22pF
Mini-Circuits
TT1-6-KK81
or Equivalent
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
ADS802
10
SBAS039B
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