time, the falling edge of HOLDB takes place just before the
falling edge of clock. One conversion requires 16 clock
cycles. Here, data is read after the next conversion is initi-
ated by HOLDB. To read data from channel B, A1 is set
high and A2 is low. As A0 is low during the first reading (A2
A1 A0 = 010) data B0 is put to the output. Before the second
RD, A0 switches high (A2 A1 A0 = 011) so data from
channel B1 is read.
DATA CHANNEL
DB14
DB13
DB12
A0
A1
B0
B1
C0
C1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
TABLE I. Channel Truth Table.
READING DATA (RD, CS)—In general, the channel/data
outputs are in tristate. Both, CS and RD have to be LOW to
enable these outputs. RD and CS have to stay LOW together
for at least 30ns (Figure 10, t13) before the output data is
valid. RD has to remain high for at least 30ns (Figure 10, t14)
before bringing it back LOW for a subsequent read com-
mand.
BYTE—If there is only an 8-bit bus available on a board
then Byte can be set HIGH (see Figures 11 and 12). In this
case, the lower eight bits can be read at the output pins DB7
to DB0 at the first RD signal and the higher bits after the
second RD signal.
12.5 clock-cycles after the start of a conversion (BUSY
going LOW), the new data is latched into its output register.
If a read process is initiated around 12.5 clock cycles after
BUSY went LOW, RD and CS should stay LOW for at least
50ns to get the new data stored to its register and switched
to the output.
GETTING DATA
The ADS7864 has three different output modes that are
selected with A2, A1 and A0.
With (A2 A1 A0) = 000 to 101 a particular channel can
directly be addressed (see Table II and Figure 9). The
channel address should be set at least 10ns (Figure 10, t12)
before the falling edge of RD and should not change as long
as RD is low.
CS being LOW tells the ADS7864 that the bus on the board
is assigned to the ADS7864. If an A/D converter shares a bus
with digital gates, there is a possibility, that digital (high
frequency) noise gets coupled into the A/D converter. If the
bus is just used by the ADS7864, CS can be hardwired to
ground. Reading data at the falling edge of one of the hold
signals might cause distortion of hold value.
CHANNEL SELECTED/
MODE
A2
A1
A0
A0
A1
B0
B1
C0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
OUTPUT CODE (DB15…DB0)
The ADS7864 has a 16 bit output word. DB15 is 1 if the
output contains valid data. This is important for the FIFO
mode. Valid Data can be read until DB15 switches to 0.
DB14, DB13 and DB12 store channel information as indi-
cated in Table I (Channel Truth Table). The 12 bit output
data is stored from DB11 (MSB) to DB0 (LSB).
C1
1
1
1
0
1
1
1
0
1
Cycle Mode
FIFO Mode
TABLE II. Address/Mode Truth Table.
BUSY
CLOCK
t1
t4
HOLDB
t13
CS
RD
t14
t12
A0
FIGURE 10. Timing for Reading Data.
®
ADS7864
12
BB [ BURR-BROWN CORPORATION ]
