START OF A CONVERSION
In the example of Figure 8, the signal HOLDB goes low first
and channel B0 and B1 will be converted first. The falling
edges of HOLDA and HOLDC occur within the same clock
cycle. Therefore, the channels A0 and A1 will be converted
as soon as the channels B0 and B1 are finished (plus
acquisition time). When the A-channels are finished, the
C-channels will be converted. The second HOLDA signal is
ignored, as the A-channels are not converted at this point in
time.
By bringing one or all of the HOLDX signals low, the input
data of the corresponding channel X is immediately placed
in the hold mode (5ns). The conversion of this channel X
follows as soon as the AD-converter is available for the
particular channel. If other channels are already in the hold
mode but not converted, then the conversion of channel X is
put in the queue until the previous conversion has been
completed. If more than one channel goes into hold mode
within one clock cycle, then channel A will be converted
first if HOLDA is one of the triggered hold signals. Next
channel B will be converted and at last channel C. If it
is important to detect a hold command during a certain
clock-cycle, then the falling edge of the hold signal has to
occur at least 10ns before the falling edge of clock. (Figure
8, t1). The hold signal can remain low without initiating a
new conversion. The hold signal has to be high for at least
15ns (Figure 8, t2) before it is brought low again and hold
has to stay low for at least 20ns (Figure 8, t3).
Once a particular hold signal goes low, further impulses of
this hold signal are ignored until the conversion is finished
or the part is reset. When the conversion is finished (BUSY
signal goes high) the sampling switches will close and
sample the selected channel. The start of the next conversion
must be delayed to allow the input capacitor of the ADS7864
to be fully charged. This delay time depends on the driving
amplifier, but should be at least 175ns (Figure 9, t4).
The ADS7864 can also convert one channel continuously, as
it is shown in Figure 9 with channel B. Therefore, HOLDA
and HOLDC are kept high all the time. To gain acquisition
TIMING SPECIFICATIONS
t6
t1
CLOCK
HOLDA
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t7
t5
t1
HOLD (A, B, C) before
falling edge of clock
10
ns
t3
t2
HOLD HIGH time to be
recognized again
15
ns
t3
t4
HOLD LOW time
Input capacitor charge time
Clock period
20
175
125
40
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
HOLDB
HOLDC
t9
t5
t6
Clock HIGH time
t7
Clock LOW time
40
t2
t8
Reset pulse width
20
t9
First hold after reset
Conversion time
20
t10
t11
t12
t13
t14
12.5 • t5
t8
RESET
Successive conversion time (16 • t5)
Address setup before RD
CS before end of RD
RD HIGH time
2
10
30
30
FIGURE 8. Start of the Conversion.
t11
t10
BUSY
t4
CLOCK
HOLDB
CS
RD
A0
FIGURE 9. Timing of One Conversion Cycle.
®
11
ADS7864
BB [ BURR-BROWN CORPORATION ]
