At time tA (Figure 13) the ADS7864 resets. With the reset
signal all conversions and scheduled conversions are can-
celled. The data in the output registers are also cleared. With
a reset a running conversion gets interrupted and all chan-
nels go into the sample mode again.
The 16 bit output word has following structure:
Valid
Data
3-Bit Channel
Information
12-Bit Data Word
Bit 15 shows if the FIFO is empty (low) or if it contains
channel information (high). Bit 12 to 14 contain the Channel
for the 12 bit data word (Bit 0 to 11). If the data is from
channel A0, then bits 14 to 12 are 000. The Channel bit
pattern is outlined in Table I (Channel Truth Table).
At time tB a HOLDB signal occurs. With the next falling
clock edge (tC) the ADS7864 puts channel B into the loop to
be converted next. As the reset signal occurred at tA, the
conversion of channel B will be started with the next rising
edge of the clock after tC.
New data is always written into the next available register. At
t0 (see Figure 14), the reset deletes all the existing data. At t1
the new data of the channels A0 and A1 are put into registers
0 and 1. On t2 the read process of channel A0 data is finished.
Therefore this data is dumped and A1 data is shifted to register
0. At t3 new data is available, this time from channel B0 and
B1. This data is written into the next available registers
(register 1 and 2). The new data of channel C0 and C1 at t4 is
put on top (registers 3 and 4).
Within the next clock cycle (tC to tF), HOLDC (tD) and
HOLDA (tE) occur. If more than one hold signals get active
within one clock cycle, channel A will be converted first. So
as soon as the conversion of channel B is done, the conver-
sion of channel A will be initiated. After this second conver-
sion, channel C will be converted.
RESET
CLOCK
HOLDA
HOLDB
HOLDC
tA
tB
tC
tD tE tF
FIGURE 13. Example of Hold Signals.
RESET
Conversion
Channel A
Conversion
Channel B
Conversion
Channel C
BUSY
RD
reg. 5
reg. 4
reg. 2
reg. 3
reg. 1
reg. 0
empty
empty
empty
empty
empty
empty
empty
empty
empty
empty
ch A1
ch A0
empty
empty
empty
empty
ch B1
ch B0
ch A1
empty
ch C1
ch C0
ch B1
ch B0
ch A1
empty
empty
empty
empty
ch A1
t0
t1
t2
t3
t4
FIGURE 14. Functionality Diagram of FIFO Registers.
®
ADS7864
14
BB [ BURR-BROWN CORPORATION ]
