ADS7863
www.ti.com
SBAS383–JUNE 2007
MODE II
(instead of 16 cycles, if M1 = 0), the ADS7863
requires 1μs to perform a complete conversion/read
cycle. If the CONVST signal is issued every 0.5μs
(which is required for the RD signal) as in Mode I,
every second pulse is ignored; see Figure 17.
With M0 = 0 and M1 set to '1', the ADS7863 also
operates in manual channel control mode and
outputs data on the SDOA pin only while SDOB is
set to tri-state. All other pins function in the same
manner as they do in Mode I. Because it takes 32
clock cycles to output the results from both ADCs
The output data consist of a '0' followed by an ADC
indicator ('0' for CHAx or '1' for CHBx), 12 bits of
conversion results, and another '00'.
16
1
16
1
16
1
16
1
16
1
1
1
CLOCK
CONVST
SDI
Every 2nd
Every 2nd
Every 2nd
CONVST
Is Ignored
CONVST
Is Ignored
CONVST
Is Ignored
C[1:0] = '00' ® CHx0 Next
C[1:0] = '11' ® CHx1 Next
P[1:0] = '11' ® No Features
C[1:0] = '00' ® CHx0 Next
P[1:0] = '00' ® No Features
C[1:0] = '11' ® CHx1 Next
P[1:0] = '11' ® No Features
SDI Ignored
SDI Ignored
P[1:0] = '00' ® No Features
M0
M1
RD
CS
CHx
B
B
Previous 12-Bit
Data CHAx
12-Bit
A
12-Bit
12-Bit
A
12-Bit
12-Bit
A
SDOA
SDOB
BUSY
Data CHA0
Data CHB0
Data CHA1
Data CHB1
Data CHA0
CHx
High-Z
Previous 12-Bit
Data CHBx
Data CHBx
No Conversion,
No Conversion,
Previous Conversion
of Both CHxx
Conversion
Conversion
Conversion
Read Access Only
Read Access Only
of Both CHx0
of Both CHx1
of Both CHx0
0ms
0.5ms
1.0ms
1.5ms
2.0ms
2.5ms
3.0ms
Figure 17. Mode II Timing Diagram (M0 = 0; M1 = 1)
15
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