ADS7863
www.ti.com
SBAS383–JUNE 2007
With tACQ = 125ns, the minimum bandwidth of the
driving amplifier is 11.5MHz. The required bandwidth
can be lower if the application allows a longer
acquisition time.
CLOCK
The ADC uses an external clock in the range of
1MHz to 24MHz. 12 clock cycles are needed for a
complete conversion; one additional clock cycle is
used for pre-charging the sample capacitors. With a
minimum of 16 clocks required per conversion, three
clock cycles are used for sampling.
A gain error occurs if a given application does not
fulfill the settling requirement shown in Equation 1.
As a result of precharging the capacitors, linearity
and THD are not directly affected.
The CLOCK duty cycle should be 50%. However, the
The
OPA365
from
Texas
Instruments
is
ADS7863 functions properly with
between 30% and 70%.
a duty cycle
recommended; in addition to offering the required
bandwidth, it provides a low offset and also offers
excellent THD performance.
RESET
The phase margin of the driving operational amplifier
is usually reduced by the ADC sampling capacitor. A
resistor placed between the capacitor and the
amplifier limits this effect; therefore, an internal 200Ω
resistor (RSER) is placed in series with the switch.
The switch resistance (RSW) is typically 50Ω (see
Equivalent Input Circuit).
The ADS7863 features an internal power-on reset
(POR) function. However, an external reset can also
be issued using SDI Register bits A[2:0] (see the
Digital section).
REFIN
The reference input is not buffered and is directly
connected to the ADC. The converter generates
spikes on the reference input voltage because of
internal switching. Therefore, an external capacitor to
the analog ground (AGND) should be used to
stabilize the reference input voltage. This capacitor
should be at least 470nF. Ceramic capacitors (X5R
type) with values up to 1μF are commonly available
as SMD in 0402 size.
The differential input voltage range of the ADC is
±VREF, the voltage at the REFIN pin.
It is important to keep the voltage to all inputs within
the 0.3V limit below AGND and above AVDD while
not allowing dc current to flow through the inputs.
Current is only necessary to recharge the
sample-and-hold capacitors.
Analog-to-Digital Converter (ADC)
REFOUT
The ADS7863 includes two SAR-type, 1.5MSPS,
12-bit ADCs (shown in the Functional Block Diagram
on the front page of this data sheet).
The ADS7863 includes a low-drift, 2.5V internal
reference source. This source feeds a 10-bit string
DAC that is controlled via the serial interface. As a
result of this architecture, the voltage at the REFOUT
pin is programmable in 2.44mV steps and can be
adjusted to specific application requirements without
the use of additional external components.
CONVST
The analog inputs are held with the rising edge of the
CONVST (conversion start) signal. The setup time of
CONVST referred to the next rising edge of CLOCK
(system clock) is 12ns (minimum). The conversion
automatically starts with the rising CLOCK edge.
CONVST should not be issued during a conversion,
that is, when BUSY is high.
However, the DAC output voltage should not be
programmed below 0.5V to ensure the correct
functionality of the reference output buffer. This
buffer is connected between the DAC and the
REFOUT pin, and is capable of driving the capacitor
at the REFIN pin. A minimum of 470nF is required to
keep the reference stable (see the previous
discussion of REFIN above). For applications that use
an external reference source, the internal reference
can be disabled using bit RP in the SDI Register
(see the Digital section). The settling time of the
REFOUT pin is 100μs. The default value of the
REFOUT pin after power-up is 2.5V.
RD (read data) and CONVST can be shorted to
minimize necessary software and wiring. The RD
signal is triggered by the ADS7863 on the falling
edge of CLOCK. Therefore, the combined signals
must be activated with the rising CLOCK edge. The
conversion then starts with the subsequent rising
CLOCK edge.
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