LAYOUT
Test Point
For optimum performance, care should be taken with the
physical layout of the ADS7852 circuitry. This is particu-
larly true if the CLK input is approaching the maximum
throughput rate.
VCC
t
dis Waveform 2, ten
3kΩ
DOUT
tdis Waveform 1
100pF
CLOAD
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic, or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in times with respect to the CLK input.
Load Circuit for tdis and ten
VIH
CS/SHDN
DOUT
90%
Waveform 1(1)
tdis
DOUT
Waveform 2(2)
With this in mind, power to the ADS7852 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low pass filter a noisy supply. The ADS7852 draws very
little current from an external reference on average as the
reference voltage is internally buffered. However, glitches
from the conversion process appear at the VREF input and the
reference source must be able to handle this. Whether the
reference is internal or external, the VREF pin should be
bypassed with a 0.1µF capacitor. An additional larger ca-
pacitor may also be used, if desired. If the reference voltage
is external and originates from an op amp, make sure it can
drive the bypass capacitor or capacitors without oscillation.
10%
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal
conditions such that the output is HIGH unless disabled
by the output control. (2) Waveform 2 is for an output
with internal conditions such that the output is LOW
unless disabled by the output control.
FIGURE 5. Timing Diagram and Test Circuits for Param-
eters in Figure 2.
In addition to using the address pins in conjunction with RD,
the power-down mode can also be terminated implicitly by
starting a new conversion (e.g., taking WR LOW while CS
is LOW). If it is desired to keep the ADS7852 in a power-
down state for a period that is greater than dictated by the
sampling rate, the convert signal driving the WR pin must be
disabled.
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connec-
tions which are too near the grounding point of a microcontroller
or digital signal processor. If needed, run a ground trace
directly from the converter to the power supply entry point.
The ideal layout will include an analog ground plane dedicated
to the converter and associated analog circuitry.
The typical supply current of the ADS7852, with a 5V
supply and a 500kHz sampling rate, is 2.6mA. In the Nap
mode, the typical supply current is 600µA. In the Sleep
mode, the current is typically reduced to 10µA.
®
13
ADS7852
BB [ BURR-BROWN CORPORATION ]
