HOLD
1
tCKH
tCKP
CLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
tCKL
t4
t1
t2
WR
CS
t4
t3
t5
Conversion n
tCONV
Conversion n + 1
BUSY
RD
tACQ
t6
t7
t8
Address
Bus
Address n + 1
Hi-Z
Address n + 2
Hi-Z
t9
t10
Data
Valid
Data
Valid
Data
Bus
Hi-Z
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tCONV
tACQ
tCKP
tCKL
tCKH
t1
Conversion Time
Acquisition Time
Clock Period
Clock LOW
1.75
0.25
5000
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
125
40
40
35
20
20
25
20
25
5
Clock HIGH
WR LOW Prior to Rising Edge of CLK
WR LOW After Rising Edge of CLK
CS LOW After Rising Edge of CLK
CS and RD HIGH
t2
t3
t4
t5
BUSY Delay After CS LOW
RD LOW
t6
t7
Address Hold Time
t8
Address Setup Time
5
t9
Bus Access Time
30
5
t10
t11
t12
t13
t14
t15
Bus Relinquish Time
CS to RD Setup Time
RD to CS Hold Time
0
0
CLK LOW to BUSY HIGH
BUSY to RD Delay
10
0
RD HIGH to CLK LOW
50
FIGURE 2. ADS7852 Write/Read Timing.
READING DATA
DIGITAL OUTPUT
STRAIGHT BINARY
Data from the ADS7852 will appear at pins 15 through 26.
The MSB will output on pin 15 while the LSB will output
on pin 26. The outputs are coded in Straight Binary (with
0V = 000H and 5V = FFFH). Following a conversion, the
BUSY pin will go HIGH. After BUSY has been HIGH for
at least t14 seconds, the CS and RD pins may be brought
LOW to enable the 12-bit output bus. CS and RD must be
held LOW for at least 25ns following BUSY HIGH. Data
will be valid 30ns after the falling edge of both CS and RD.
The output data will remain valid for 20ns following the
rising edge of both CS and RD. See Figure 2 for the read
cycle timing diagram.
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
Least Significant
Bit (LSB)
1.2207mV
Full Scale
4.99878V
2.5V
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
FFF
800
7FF
000
Midscale
Midscale –1LSB
Zero Full Scale
2.49878V
0V
Table I. Ideal Input Voltages and Output Codes.
®
11
ADS7852
BB [ BURR-BROWN CORPORATION ]
