The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the power-
down mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW,
the device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be
valid.
PD1
0
PD0
0
Description
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
0
1
1
1
0
1
Reserved for future use.
Reserved for future use.
No power-down between conversions, device al-
ways powered.
TABLE V. Power-Down Selection.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
1.5
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16-Clocks per Conversion
tDH
The control bits for conversion n+1 can be overlapped with
conversion ‘n’ to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. In addition, the
ADS7841 is fully powered while other serial communica-
tions are taking place.
tDO
tDV
200
200
200
tTR
tCSS
tCSH
tCH
100
0
200
200
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
tBDV
tBTR
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
Digital Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7841.
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
900
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
10
tDO
tDV
100
70
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7841.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
tTR
70
tCSS
tCSH
tCH
50
0
150
150
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
100
70
tBDV
tBTR
70
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
DCLK
1
15
1
15
1
SGL/
SGL/
DIF
DIN
BUSY
DOUT
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0
DIF
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
®
ADS7841
12
BB [ BURR-BROWN CORPORATION ]
