CS
DCLK
DIN
tACQ
1
8
1
8
1
8
SGL/
DIF
S
A2 A1 A0 MODE
Idle
PD1 PD0
Acquire
(START)
Conversion
Idle
BUSY
DOUT
11 10
(MSB)
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
CS
DCLK
1
8
1
8
1
8
1
DIN
BUSY
DOUT
S
S
CONTROL BITS
CONTROL BITS
11 10
9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 5. Detailed Timing Diagram.
®
ADS7841
11