the device is in the sample or hold mode. When sampling,
the input has a 4kΩ input impedance to the reference. The
source of the analog input voltage must be able to charge the
input impedance (typically 25pF || 1kΩ) to a 12-bit settling
level within the same period. This can be as little as 350ns
in some operating modes. When the converter is in the hold
mode, the input impedance switches to approximately 2kΩ
to ground.
THEORY OF OPERATION
The ADS7835 is a high speed Successive Approximation
Register (SAR) analog-to-digital converter (A/D) with an
internal 2.5V bandgap reference. The architecture is based
on capacitive redistribution which inherently includes a S/H
function. The converter is fabricated on a 0.6µ CMOS
process. See Figure 1 for the basic operating circuit for the
ADS7835.
Care must be taken regarding the input voltage on the AIN
pin. The input signal should remain within –5.3V and +5.3V
(with a 5V supply) to avoid damaging the converter.
The ADS7835 requires an external clock to run the conver-
sion process. This clock can vary between 200kHz (12.5kHz
throughput) and 8MHz (500kHz throughput). The duty cycle
of the clock is unimportant as long as the minimum HIGH
and LOW times are at least 50ns and the clock period is at
least 125ns. The minimum clock frequency is set by the
leakage on the capacitors internal to the ADS7835.
REFERENCE
The reference voltage on the VREF pin directly sets the full-
scale range of the analog input. The ADS7835 can operate
with a reference in the range of 2.3V to 2.9V, for a full-scale
range of ±2.3V to ±2.9V.
The analog input to the ADS7835 is single-ended. The
ADS7835 provides a true bipolar input where the input will
swing below ground. When using the internal 2.5V refer-
ence the input range is ±2.5V (within ±20mV for the low
grade and ±12mV for the high grade). When using an
external reference the input range is –VREF to +VREF. The
ADS7835 will accept an external reference with a range of
2.3V to 2.9V.
The voltage at the VREF pin is internally buffered and this
buffer drives the CDAC portion of the converter. This is
important because the buffer greatly reduces the dynamic
load placed on the reference source. However, the voltage at
VREF will still contain some noise and glitches from the SAR
conversion process. These can be reduced by carefully
bypassing the VREF pin to ground as outlined in the sections
that follow.
The digital result of the conversion is provided in a serial
manner, synchronous to the CLK input. The provided result
is Most Significant Bit (MSB) first and represents the result
of the conversion currently in progress—there is no pipeline
delay. By properly controlling the CONV and CLK inputs,
it is possible to obtain the digital result Least Significant Bit
(LSB) first.
INTERNAL REFERENCE
The ADS7835 contains an on-board 2.5V reference, result-
ing in a –2.5V to +2.5V input range on the analog input. The
Specification table gives the various specifications for the
internal reference. This reference can be used to supply a
small amount of source current to an external load, but the
load should be static. Due to the internal 10kΩ resistor, a
dynamic load will cause variations in the reference voltage,
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage
seen at the buffer input. The amount of reduction depends on
the load and the actual value of the internal “10kΩ” resistor.
The value of this resistor can vary by ±30%.
ANALOG INPUT
The analog input (pin 2) of the ADS7835 is connected to a
2kΩ x 2kΩ voltage divider. This divider allows the ADS7835
to accept bipolar inputs while operating from a single 5V
supply. The divider is connected to the output buffer of the
internal +2.5V supply. When the input is at +full-scale
(+2.5V), the voltage at the input to the CDAC (Capacitive
Digital-to-Analog Converter) is also +2.5V resulting in
negligible input current. When the input is at –full-scale
(–2.5V), the voltage at the input of the CDAC is 0V
resulting in 1.25mA of current being sourced out of the
input pin. It is recommended that a buffer be placed
between the analog input signal and the input of the ADS7835.
The VREF pin should be bypassed with a 0.1µF capacitor
placed as close as possible to the ADS7835 package. In
addition, a 2.2µF tantalum capacitor should be used in
parallel with the ceramic capacitor. Placement of this ca-
pacitor, while not critical to performance, should be placed
as close to the package as possible.
The input impedance of the ADS7835 depends on whether
+5V
+
+
ADS7835
2.2µF
0.1µF
0.1µF
10µF
1
2
3
4
VREF
+VCC
CLK
8
7
6
5
±2.5V
Analog Input
Serial Clock
Serial Data
Convert Start
AIN
from
Microcontroller
or DSP
GND
GND
DATA
CONV
FIGURE 1. Basic Operation of the ADS7835.
®
7
ADS7835
BB [ BURR-BROWN CORPORATION ]
