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ADS7835P 参数 Datasheet PDF下载

ADS7835P图片预览
型号: ADS7835P
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial Access, CMOS, PDIP8, PLASTIC, DIP-8]
分类和应用: 转换器
文件页数/大小: 13 页 / 171 K
品牌: BB [ BURR-BROWN CORPORATION ]
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logic.  
Figure 7 shows a timing diagram that might be used with a  
typical digital signal processor such as a TI DSP. For the  
Buffered Serial Port (BSP) on the TMS320C54X family,  
CONV would tied to BFSX, CLK would be tied to BCLKX,  
and DATA would be tied to BDR.  
DATA FORMAT  
The ADS7835 output data is in Binary Two’s Complement  
format as shown in Table III. This table shows the ideal  
output code for the given input voltage and does not include  
SPI/QSPI INTERFACING  
DESCRIPTION  
ANALOG INPUT  
DIGITAL OUTPUT  
Figure 8 shows the timing diagram for a typical Serial  
Peripheral Interface (SPI) or Queued Serial Peripheral Inter-  
face (QSPI). Such interfaces are found on a number of  
microcontrollers from various manufacturers. CONV would  
be tied to a general purpose I/O pin (SPI) or to a PCX pin  
(QSPI), CLK would be tied to the serial clock, and DATA  
would be tied to the serial input data pin such as MISO  
(Master In Slave Out).  
Full-Scale Input  
Range  
Least Significant Bit  
(LSB)(2)  
BINARY TWO’S  
COMPLEMENT  
(1)  
–VREF to +VREF  
BINARY  
CODE  
HEX  
CODE  
(–VREF to +VREF)/4096  
+Full Scale  
Mid-Scale  
Mid-Scale –1LSB  
–Full Scale  
2.49878V  
0V  
–0.00122V  
–2.49878V  
0111 1111 1111  
0000 0000 0000  
1111 1111 1111  
1000 0000 0000  
7FF  
000  
FFF  
800  
NOTES: (1) –2.5V to +2.5V when the internal reference is used. (2) 1.22mV  
with a 2.5V reference.  
Note the time tDRP shown in Figure 8. This represents the  
maximum amount of time between CONV going LOW and  
the start of the conversion clock. Since CONV going LOW  
places the S/H in the hold mode and because the hold  
capacitor loses charge over time, there is a requirement that  
time tDRP be met as well as the maximum clock period  
TABLE III. Ideal Input Voltages and Output Codes.  
the effects of offset, gain, or noise.  
DSP INTERFACING  
CONV  
15  
16  
1
2
3
12  
13  
14  
15  
16  
1
2
3
4
CLK  
D11  
(MSB)  
D0  
(LSB)  
D11  
(MSB)  
DATA  
D10  
D1  
D10  
D9  
FIGURE 7. Typical DSP Interface Timing.  
tDRP  
tACQ  
CONV  
1
2
3
4
13  
14  
15  
16  
1
2
3
CLK  
D11  
(MSB)  
D0  
(LSB)  
D11  
(MSB)  
DATA  
D10  
D1  
FIGURE 8. Typical SPI/QSPI Interface Timing.  
®
ADS7835  
12