CONV
CLK
1
2
3
12
13
D11
(MSB)
D0
(LSB)
DATA
D10
D1
tCVSP
tACQ
SAMPLE/HOLD
MODE
SAMPLE
HOLD
SAMPLE
HOLD
(3)
INTERNAL
CONVERSION
STATE
IDLE
CONVERSION IN PROGRESS
IDLE
tCVPU
tCKPD
POWER MODE
FULL POWER
LOW POWER
FULL POWER
(1)
(2)
NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the
start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH. (3) When in power-down, the transition from
hold mode to sample mode is initiated by CONV going HIGH.
FIGURE 4. Power-Down Timing.
tCVH
CONV
tCKCH
1
2
3
12
13
14
23
24
CLK
tCKCS
tCVDD
D11
(MSB)
D0
(LSB)
D11
(MSB)
DATA
D10
D1
D1
D10
LOW...
(1)
(2)
SAMPLE/HOLD
MODE
SAMPLE
HOLD
INTERNAL
CONVERSION
STATE
IDLE
CONVERSION IN PROGRESS
tCVPD
IDLE
POWER MODE
FULL POWER
LOW POWER
(3)
NOTES: (1) The serial data can be transmitted LSB-first by pulling CONV LOW during the 13th clock cycle. (2) After the MSB has been
transmitted, the DATA output pin will remain LOW until CONV goes HIGH. (3) When CONV is taken LOW to initiate the LSB first transfer,
the converter enters the power-down mode.
FIGURE 5. Serial Data “LSB-First” Timing.
typical performance curve “Supply Current vs Sample Rate.”
in power-down an increasing percentage of time. This re-
duces total power consumption by a considerable amount.
For example, a 50kHz conversion rate results in roughly
1/10 of the power (minus the reference) that is used at a
In contrast, the second method (clocking at a fixed rate)
means that each conversion takes X clock cycles. As the
time between conversions get longer, the converter remains
®
ADS7835
10
BB [ BURR-BROWN CORPORATION ]
