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ADS7821PB 参数 Datasheet PDF下载

ADS7821PB图片预览
型号: ADS7821PB
PDF下载: 下载PDF文件 查看货源
内容描述: 16位10ms的采样CMOS模拟数字转换器 [16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 10 页 / 282 K
品牌: BB [ BURR-BROWN CORPORATION ]
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PARALLEL OUTPUT (During a Conversion)  
READING DATA  
After conversion ‘n’ has been initiated, valid data from  
conversion ‘n-1’ can be read and will be valid up to 5µs after  
the start of conversion ‘n’. Do not attempt to read data from  
5µs after the start of conversion ‘n’ until BUSY (pin 26)  
goes HIGH; this may result in reading invalid data. Refer to  
Table IV and Figures 3 through 5 for timing specifications.  
The ADS7821 outputs full or byte-reading parallel data in  
Straight Binary data output format. The parallel output will  
be active when R/C (pin 24) is HIGH and CS (pin 25) is  
LOW. Any other combination of CS and R/C will tri-state  
the parallel output. Valid conversion data can be read in a  
full parallel, 16-bit word or two 8-bit bytes on pins 6-13 and  
pins 15-22. BYTE (pin 23) can be toggled to read both bytes  
within one conversion cycle. Refer to Table III for ideal  
output codes and Figure 2 for bit locations relative to the  
state of BYTE.  
Note! For the best possible performance, data should not be  
read during a conversion. The switching noise of the asyn-  
chronous data transfer can cause digital feedthrough degrad-  
ing the converter’s performance.  
The number of control lines can be reduced by tying CS  
LOW while using R/C to initiate conversions and activate  
the output mode of the converter. See Figure 3.  
DIGITAL OUTPUT  
STRAIGHT BINARY  
DESCRIPTION  
ANALOG INPUT  
0 to +5V  
BINARY CODE  
HEX CODE  
Full Scale Range  
SYMBOL  
DESCRIPTION  
MIN TYP MAX UNITS  
Least Significant  
Bit (LSB)  
76µV  
t1  
t2  
Convert Pulse Width  
40  
5000  
8
ns  
Data Valid Delay  
after Start of Conversion  
µs  
Full Scale  
Midscale  
4.999924V  
2.5V  
1111 1111 1111 1111  
1000 0000 0000 0000  
0111 1111 1111 1111  
FFFF  
8000  
7FFF  
t3  
BUSY Delay  
from Start of Conversion  
65  
8
ns  
One LSB below  
Midscale  
2.499924V  
t4  
t5  
BUSY LOW  
µs  
Zero Scale  
0V  
0000 0000 0000 0000  
0000  
BUSY Delay after  
End of Conversion  
220  
ns  
Table III. Ideal Input Voltages and Output Codes.  
t6  
t7  
Aperture Delay  
Conversion Time  
40  
ns  
µs  
µs  
ns  
ns  
µs  
7.6  
8
2
PARALLEL OUTPUT (After a Conversion)  
t8  
Acquisition Time  
t9  
Bus Relinquish Time  
BUSY Delay after Data Valid  
10  
35  
83  
After conversion ‘n’ is completed and the output registers  
have been updated, BUSY (pin 26) will go HIGH. Valid data  
from conversion ‘n’ will be available on D15-D0 (pin 6-13  
and 15-22). BUSY going HIGH can be used to latch the  
data. Refer to Table IV and Figures 3 through 5 for timing  
specifications.  
t10  
t11  
50 200  
5
Previous Data Valid  
after Start of Conversion  
t
7 + t6  
t12  
Throughput Time  
R/C to CS Setup Time  
Time Between Conversions  
9
10  
83  
µs  
ns  
µs  
ns  
10  
t13  
10  
t14  
Bus Access Time  
and BYTE Delay  
10  
TABLE IV. Conversion Timing.  
BYTE LOW  
BYTE HIGH  
+5V  
6
7
23  
22  
21  
20  
19  
18  
17  
16  
15  
6
7
23  
22  
21  
20  
19  
18  
17  
16  
15  
Bit 15 (MSB)  
Bit 14  
Bit 13  
Bit 12  
Bit 11  
Bit 10  
Bit 9  
Bit 7  
Bit 6  
Bit 0 (LSB)  
Bit 1  
Bit 8  
Bit 9  
ADS7821  
ADS7821  
8
8
Bit 5  
9
9
Bit 2  
Bit 4  
Bit 10  
Bit 11  
Bit 12  
Bit 13  
Bit 14  
10  
11  
12  
13  
14  
10  
11  
12  
13  
14  
Bit 3  
Bit 3  
Bit 4  
Bit 2  
Bit 5  
Bit 1  
Bit 8  
Bit 6  
Bit 0 (LSB)  
Bit 7  
Bit 15 (MSB)  
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).  
®
7
ADS7821