There is an important distinction between the power down
mode that is entered after a conversion is complete and the
full power down mode which is enabled when CS is HIGH.
While both power down the analog section, the digital section
is powered down only when CS is HIGH. Thus, if CS is left
LOW at the end of a conversion and the converter is continu-
ally clocked, the power consumption will not be as low as
when CS is HIGH. See Figure 8 for more information.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7817 circuitry. This is particularly
true if the reference voltage is low and/or the conversion rate
is high. At 200kHz conversion rate, the ADS7817 makes a bit
decision every 312ns. That is, for each subsequent bit deci-
sion, the digital output must be updated with the results of the
last bit decision, the capacitor array appropriately switched
and charged, and the input to the comparator settled to a
12-bit level all within one clock cycle.
By lowering the reference voltage, the ADS7817 requires
less current to completely charge its internal capacitors on
both the analog input and the reference input. This reduction
in power dissipation should be weighed carefully against the
resulting increase in noise, offset, and gain error as outlined
in the Reference section.
The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during
any single conversion for an n-bit SAR converter, there are
n “windows” in which large external transient voltages can
easily affect the conversion result. Such spikes might origi-
nate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter’s DCLOCK signal—as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.
60
TA = 25°C
VCC = +5V
VREF = +2.5V
50
fCLK = 16 • fSAMPLE
CS LOW
(GND)
40
30
20
10
0
With this in mind, power to the ADS7817 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the ADS7817 package as possible. In
addition, a 1 to 10µF capacitor and a 10Ω series resistor may
be used to lowpass filter a noisy supply.
CS = HIGH (VCC
)
1
10
100
1000
Sample Rate (kHz)
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the op-
amp can drive the bypass capacitor without oscillation (the
series resistor can help in this case). Keep in mind that while
the ADS7817 draws very little current from the reference on
average, there are higher instantaneous current demands
placed on the external reference circuitry.
FIGURE 8. Shutdown Current is Considerably Lower with
CS HIGH than when CS is LOW.
SHORT CYCLING
Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS7817 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8-bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 8th bit has been clocked out.
Also, keep in mind that the ADS7817 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference voltage is derived from the power supply. Any
noise and ripple from the supply that is not rejected by the
external reference circuitry will appear directly in the digital
results. While high frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to
line frequency (50Hz or 60Hz) can be difficult to remove.
This technique can be used to lower the power dissipation in
those applications where an analog signal is being monitored
until some condition becomes true. For example, if the
signal is outside a predetermined range, the full 12-bit
conversion result may not be needed. If so, the conversion
can be terminated after the first n-bits, where n might be as
low as 3 or 4. This results in lower power dissipation in both
the converter and the rest of the system, as they spend more
time in the power down mode.
The GND pin on the ADS7817 should be placed on a clean
ground point. In many cases, this will be the “analog”
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace di-
rectly from the converter to the power supply connection
point. The ideal layout will include an analog ground plane
for the converter and associated analog circuitry.
®
ADS7817
12
BB [ BURR-BROWN CORPORATION ]
