1.4V
VOH
VOL
3kΩ
DOUT
DOUT
Test Point
tr
tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times tr, and tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdDO
tdis Waveform 2, ten
3kΩ
DOUT
VOH
VOL
tdis Waveform 1
DOUT
100pF
CLOAD
thDO
Voltage Waveforms for DOUT Delay Times, tdDO
Load Circuit for tdis and tden
VIH
CS/SHDN
CS/SHDN
DCLOCK
DOUT
Waveform 1(1)
90%
10%
1
2
tdis
DOUT
Waveform 2(2)
VOL
DOUT
B11
ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Voltage Waveforms for ten
FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I.
1000
100
10
1000
100
10
TA = 25°C
TA = 25°C
VCC = +5V
VCC = +5V
V
REF = +2.5V
V
REF = +2.5V
f
CLK = 3.2MHz
f
CLK = 16 • fSAMPLE
1
1
1
10
Sample Rate (kHz)
100
1000
1
10
100
1000
Sample Rate (kHz)
FIGURE 6. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
FIGURE 7. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
®
ADS7817
11
BB [ BURR-BROWN CORPORATION ]
