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ADS7813UB 参数 Datasheet PDF下载

ADS7813UB图片预览
型号: ADS7813UB
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗串行16位采样模拟数字转换器 [Low-Power, Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 17 页 / 378 K
品牌: BB [ BURR-BROWN CORPORATION ]
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completed and before the next conversion starts—as shown  
in Figure 6. Note that the DATACLK signal should be static  
before the start of the next conversion. If this is not ob-  
served, the DATACLK signal could affect the voltage that  
is acquired.  
might be possible to use the rising edge of the DATACLK  
signal. However, one extra clock period (not shown in  
Figures 6, 7, and 8) is needed for the final bit.  
The external DATACLK signal must be LOW or CS must  
be HIGH prior to BUSY rising (see time t25 in Figures 7 and  
8). If this is not observed during this time, the output shift  
register of the ADS7813 will not be updated with the  
conversion result. Instead, the previous contents of the shift  
register will remain and the new result will be lost.  
External DATACLK Active During the Next Conversion  
Another method of obtaining the conversion result is shown  
in Figure 7. Since the output shift register is not updated  
until the end of the conversion, the previous result remains  
valid during the next conversion. If a fast clock (2MHz)  
can be provided to the ADS7813, the result can be read  
during time t2. During this time, the noise from the  
DATACLK signal is less likely to affect the conversion  
result.  
Before reading the next three paragraphs, consult the Sensi-  
tivity to External Digital Signals section of this data sheet.  
This will explain many of the concerns regarding how and  
when to apply the external DATACLK signal.  
External DATACLK Active After the Conversion  
The preferred method of obtaining the conversion result is to  
provide the DATACLK signal after the conversion has been  
t1  
t2  
CONV  
BUSY  
t21  
t24  
t23  
t25  
DATACLK  
DATA  
1
2
3
4
15  
16  
1
t19  
t20  
t22  
MSB  
Bit 14  
Bit 13  
Bit 1  
LSB  
MSB  
FIGURE 7. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT HIGH,  
CS LOW).  
CONV  
BUSY  
t5  
t4  
t24  
t25  
DATACLK  
DATA  
1
2
n
n+1  
15  
16  
Bit n-1  
MSB  
Bit 14  
Bit n  
Bit 1  
LSB  
FIGURE 8. Serial Data Timing, External Clock, Clocking After the Conversion Completes and During the Next Conversion  
(EXT/INT HIGH, CS LOW).  
®
11  
ADS7813  
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