QSPI™ INTERFACING
QSPI™
ADS7807
+5V
Figure 14 shows a simple interface between the ADS7807
and any QSPI equipped microcontroller. This interface as-
sumes that the convert pulse does not originate from the
microcontroller and that the ADS7807 is the only serial
peripheral.
R/C
CS
EXT/INT
PCS0
PCS1
SCK
DATACLK
D7 (MSB)
Before enabling the QSPI interface, the microcontroller must
be configured to monitor the slave select line. When a
MISO
transition from LOW to HIGH occurs on Slave Select (SS
)
from BUSY (indicating the end of the current conversion), the
port can be enabled. If this is not done, the microcontroller
and the A/D converter may be “out-of-sync”.
BYTE
CPOL = 0
CPHA = 0
QSPI is a registered trademark of Motorola.
Convert Pulse
FIGURE 15. QSPI Interface to the ADS7807. Processor
Initiates Conversions.
QSPI™
ADS7807
For both transfers, the DT register (delay after transfer) is
used to cause a 19µs delay. The interface is also set up to
wrap to the beginning of the queue. In this manner, the QSPI
is a state machine which generates the appropriate timing for
the ADS7807. This timing is thus locked to the crystal-based
timing of the microcontroller and not interrupt driven. So, this
interface is appropriate for both AC and DC measurements.
R/C
PCS0/SS
BUSY
MOSI
SCK
SDATA
DATACLK
CS
For the fastest conversion rate, the baud rate should be set
to 2 (4.19MHz SCK), DT set to 10, the first serial transfer set
to 8 bits, the second set to 16 bits, and DSCK disabled (in the
command control byte). This will allow for a 23kHz maximum
conversion rate. For slower rates, DT should be increased.
Do not slow SCK as this may increase the chance of
affecting the conversion results or accidently initiating a
second conversion during the first 8-bit transfer.
EXT/INT
BYTE
CPOL = 0 (Inactive State is LOW)
CPHA = 1 (Data valid on falling edge)
QSPI port is in slave mode.
QSPI is a registered trademark of Motorola.
FIGURE 14. QSPI Interface to the ADS7807.
In addition, CPOL and CPHA should be set to zero (SCK
normally LOW and data captured on the rising edge). The
command control byte for the 8-bit transfer should be set to
20H and for the 16-bit transfer to 61H.
Figure 15 shows another interface between the ADS7807
and a QSPI equipped microcontroller which allows the
microcontroller to give the convert pulses while also allowing
multiple peripherals to be connected to the serial bus. This
interface and the following discussion assume a master clock
for the QSPI interface of 16.78MHz. Notice that the serial
data input of the microcontroller is tied to the MSB (D7) of the
ADS7807 instead of the serial output (SDATA). Using D7
instead of the serial port offers tri-state capability which
allows other peripherals to be connected to the MISO pin.
When communication is desired with those peripherals, PCS0
and PCS1 should be left HIGH; that will keep D7 tri-stated.
SPI™ INTERFACE
The SPI interface is generally only capable of 8-bit data
transfers. For some microcontrollers with SPI interfaces, it
might be possible to receive data in a similar manner as
shown for the QSPI interface in Figure 14. The microcontroller
will need to fetch the 8 most significant bits before the
contents are overwritten by the least significant bits.
A modified version of the QSPI interface shown in Figure 15
might be possible. For most microcontrollers with SPI inter-
face, the automatic generation of the start-of-conversion
pulse will be impossible and will have to be done with
software. This will limit the interface to ‘DC’ applications due
to the insufficient jitter performance of the convert pulse
itself.
In this configuration, the QSPI interface is actually set to do
two different serial transfers. The first, an 8-bit transfer, causes
PCS0 (R/C) and PCS1 (CS) to go LOW, starting a conver-
sion. The second, a 16-bit transfer, causes only PCS1 (CS) to
go LOW. This is when the valid data will be transferred.
QSPI is a registered trademark of Motorola.
SPI is a registered trademark of Motorola.
ADS7807
18
SBAS022C
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