clock pulse. As a result, data can be read on the parallel port
prior to reading the same data on the serial port, but data
cannot be read through the serial port prior to reading the
same data on the parallel port.
PARALLEL OUTPUT (AFTER A CONVERSION)
After conversion ‘n’ is completed and the output registers
have been updated,
BUSY
(pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13 and
15-17).
BUSY
going high can be used to latch the data. Refer
to Table V and Figures 2 and 3 for timing constraints.
PARALLEL OUTPUT
To use the parallel output, tie
EXT/INT
(pin 8) HIGH and
DATACLK (pin 18) LOW. SDATA (pin 19) should be left
unconnected. The parallel output will be active when
R/C
(pin
22) is HIGH and
CS
(pin 23) is LOW. Any other combination
of
CS
and
R/C
will tri-state the parallel output. Valid conver-
sion data can be read in two 8-bit bytes on D7-D0 (pins 9-13
and 15-17). When BYTE (pin 21) is LOW, the 8 most signifi-
cant bits will be valid with the MSB on D7. When BYTE is
HIGH, the 8 least significant bits will be valid with the LSB on
D0. BYTE can be toggled to read both bytes within one
conversion cycle.
Upon initial power up, the parallel output will contain indeter-
minate data.
PARALLEL OUTPUT (DURING A CONVERSION)
After conversion ‘n’ has been initiated, valid data from con-
version ‘n – 1’ can be read and will be valid up to 12µs after
the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until
BUSY
(pin
24) goes HIGH; this may result in reading invalid data. Refer
to Table V and Figures 2 and 3 for timing constraints.
t
1
R/C
t
3
BUSY
t
6
t
7
MODE
Acquire
Convert
t
12
t
11
Parallel
Data Bus
Previous
High Byte Valid
Hi-Z
Previous High
Byte Valid
Previous Low
Byte Valid
t
2
t
9
BYTE
t
12
t
12
t
12
Not Valid
t
8
Acquire
t
4
t
5
t
1
t
3
t
6
Convert
t
12
t
10
High Byte
Valid
Low Byte
Valid
Hi-Z
t
9
t
12
High Byte
Valid
FIGURE 2. Conversion Timing with Parallel Output (CS and DATACLK tied LOW,
EXT/INT
tied HIGH).
t
21
R/C
t
1
CS
t
3
BUSY
t
21
t
21
t
21
t
21
t
21
t
4
t
21
BYTE
t
21
t
21
t
21
DATA
BUS
Hi-Z State
High Byte
t
12
Hi-Z State
t
9
Low Byte
t
12
t
9
Hi-Z State
FIGURE 3. Using
CS
to Control Conversion and Read Timing with Parallel Outputs.
ADS7807
SBAS022C
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BURR-BROWN [ BURR-BROWN CORPORATION ]
