SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
7
+ t
8
DESCRIPTION
MIN TYP MAX UNITS
19
12
20
85
20
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
Convert Pulse Width
0.04
Data Valid Delay after
R/C
LOW
BUSY
Delay from
Start of Conversion
BUSY
LOW
BUSY
Delay after
End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Bus Relinquish Time
10
BUSY
Delay after Data Valid
20
Previous Data Valid
12
after Start of Conversion
Bus Access Time and BYTE Delay
Start of Conversion
to DATACLK Delay
DATACLK Period
Data Valid to DATACLK
20
HIGH Delay
Data Valid after DATACLK
400
LOW Delay
External DATACLK Period
100
External DATACLK LOW
40
External DATACLK HIGH
50
25
CS
and
R/C
to External
DATACLK Setup Time
10
R/C
to
CS
Setup Time
Valid Data after DATACLK HIGH
25
Throughput Time
INTERNAL DATA CLOCK
(During a Conversion)
To use the internal data clock, tie
EXT/INT
(pin 8) LOW. The
combination of
R/C
(pin 22) and
CS
(pin 23) LOW will initiate
conversion ‘n’ and activate the internal data clock (typically
900kHz clock rate). The ADS7807 will output 16 bits of valid
data, MSB first, from conversion ‘n-1’ on SDATA (pin 19),
synchronized to 16 clock pulses output on DATACLK (pin 18).
The data will be valid on both the rising and falling edges of the
internal data clock. The rising edge of
BUSY
(pin 24) can be
used to latch the data. After the 16th clock pulse, DATACLK will
remain LOW until the next conversion is initiated, while SDATA
will go to whatever logic level was input on TAG (pin 20) during
the first clock pulse. Refer to Table VI and Figure 4.
19
90
40
19
20
5
83
60
19
83
1.4
1.1
75
600
EXTERNAL DATA CLOCK
To use an external data clock, tie
EXT/INT
(pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7807,
CS
(pin 23) must be LOW and
R/C
(pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
An obvious way to simplify control of the converter is to tie
CS
LOW and use
R/C
to initiate conversions.
While this is perfectly acceptable, there is a possible problem
when using an external data clock. At an indeterminate point
from 12µs after the start of conversion ‘n’ until
BUSY
rises,
the internal logic will shift the results of conversion ‘n’ into the
output register. If
CS
is LOW,
R/C
HIGH, and the external
clock is HIGH at this point, data will be lost. So, with
CS
LOW, either
R/C
and/or DATACLK must be LOW during this
period to avoid losing valid data.
25
TABLE VI. Conversion and Data Timing. T
A
= –40°C to +85°C.
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful with
the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these
pins will come out of Hi-Z state whenever
CS
(pin 23) is LOW
and
R/C
(pin 22) is HIGH. The serial output can not be tri-
stated and is always active. Refer to the Applications Infor-
mation section for specific serial interfaces.
CS or R/C
(1)
t
14
t
13
1
2
t
16
t
15
MSB Valid
SDATA
(Results from previous conversion.)
BUSY
Bit 14 Valid
Bit 13 Valid
3
t
7
+ t
8
DATACLK
15
16
1
2
Bit 1 Valid
LSB Valid
MSB Valid
Bit 14 Valid
NOTE: (1) If controlling with
CS
, tie
R/C
LOW. Data bus pins will remain Hi-Z at all times.
If controlling with
R/C,
tie
CS
LOW. Data bus pins will be active when
R/C
is HIGH, and should be left unconnected.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
10
ADS7807
www.ti.com
SBAS022C
BURR-BROWN [ BURR-BROWN CORPORATION ]
