PIN DESCRIPTIONS
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
R1
IN
AGND1
R2
IN
CAP
REF
AGND2
SB/BTC
EXT/INT
D7
D6
D5
D4
D3
DGND
D2
D1
D0
DATACLK
SDATA
TAG
BYTE
R/C
CS
BUSY
PWRD
REFD
V
ANA
V
DIG
DIGITAL
I/O
DESCRIPTION
Analog Input. See Figure 7.
Analog Sense Ground.
Analog Input. See Figure 7.
Reference Buffer Output. 2.2µF tantalum capacitor to ground.
Reference Input/Output. 2.2µF tantalum capacitor to ground.
Analog Ground
Selects Straight Binary or Binary Two’s Complement for Output Data Format.
External/Internal data clock select.
Data Bit 7 if BYTE is HIGH. Data bit 15 (MSB) if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW. Leave
unconnected when using serial output.
Data Bit 6 if BYTE is HIGH. Data bit 14 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 5 if BYTE is HIGH. Data bit 13 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 4 if BYTE is HIGH. Data bit 12 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 3 if BYTE is HIGH. Data bit 11 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Digital Ground
Data Bit 2 if BYTE is HIGH. Data bit 10 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 1 if BYTE is HIGH. Data bit 9 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Bit 0 (LSB) if BYTE is HIGH. Data bit 8 if BYTE is LOW. Hi-Z when CS is HIGH and/or R/C is LOW.
Data Clock Output when EXT/INT is LOW. Data clock input when EXT/INT is HIGH.
Serial Output Synchronized to DATACLK
Serial Input When Using an External Data Clock
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH) on parallel output pins.
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C
enables the parallel output.
Internally OR’d with R/C. If R/C is LOW, a falling edge on CS initiates a new conversion. If EXT/INT is LOW, this same
falling edge will start the transmission of serial data results from the previous conversion.
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs
have been updated.
PWRD HIGH shuts down all analog circuitry except the reference. Digital circuitry remains active.
REFD HIGH shuts down the internal reference. External reference will be required for conversions.
Analog Supply. Nominally +5V. Decouple with 0.1µF ceramic and 10µF tantalum capacitors.
Digital Supply. Nominally +5V. Connect directly to pin 27. Must be
≤
V
ANA
.
I
I
O
O
O
O
O
O
O
O
I/O
O
I
I
I
I
O
I
I
PIN CONFIGURATION
Top View
DIP, SO
ANALOG
INPUT
RANGE
±10V
0V to 5V
0V to 4V
CONNECT R1
IN
VIA 200Ω
TO
V
IN
AGND
V
IN
CONNECT R2
IN
VIA 100Ω
TO
CAP
V
IN
V
IN
IMPEDANCE
45.7kΩ
20.0kΩ
21.4kΩ
R1
IN
AGND1
R2
IN
CAP
REF
AGND2
SB/BTC
EXT/INT
D7
1
2
3
4
5
6
7
ADS7807
8
9
28 V
DIG
27 V
ANA
26 REFD
25 PWRD
24 BUSY
23 CS
22 R/C
21 BYTE
20 TAG
19 SDATA
18 DATACLK
17 D0
16 D1
15 D2
TABLE I. Input Range Connections. See Figure 7.
D6 10
D5 11
D4 12
D3 13
DGND 14
4
ADS7807
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