Word 1
Word 2
DB4 DB3
DB0
Processor
Converter
DB7
DB6
DB5
DB9
DB4
DB8
DB3
DB7
DB2
DB6
DB1
DB5
DB0
DB4
DB7
DB3
DB6
DB2
DB5
DB1
DB2
0
DB1
0
DB0
0
DB11 DB10
0
FIGURE 7. 12-Bit Data Format for 8-Bit Systems.
STATUS 28
2
4
12/8
AO
DB11 (MSB) 27
26
25
24
23
22
AO
Address
Bus
Data
Bus
ADS774
21
20
19
18
17
DB0 (LSB) 16
Digital Common 15
FIGURE 8. Connection to an 8-Bit Bus.
S/H CONTROL MODE
AND ADC774 EMULATION MODE
tion is made about the input level after the convert command
arrives, since the input signal is sampled and conversion
begins immediately after the convert command. This means
that a convert command can also be used to switch an input
multiplexer or change gains on a programmable gain ampli-
fier, allowing the input signal to settle before the next
acquisition at the end of the conversion. Because aperture
jitter is minimized in the Control Mode, a high input fre-
quency can be converted without an external sample/hold.
The Emulation Mode allows the ADS774 to be dropped into
most existing ADC774 sockets without changes to other
system hardware or software. In existing sockets, the analog
input is held stable during the conversion period so that
accurate conversions can proceed, but the input can change
rapidly at any time before the conversion starts. The Emula-
tion Mode uses the stability of the analog input during the
conversion period to both acquire and convert in a maximum
of 8µs (8.5µs over temperature.) In fact, system throughput
can be increased, since the input to the ADS774 can start
slewing before the end of a conversion (after the acquisition
time), which is not possible with existing ADC774s.
In the Emulation Mode, a delay time is introduced between
the convert command and the start of conversion to allow the
ADS774 enough time to acquire the input signal before
converting. This increases the effective aperture delay time
from 0.02µs to 1.6µs, but allows the ADS774 to replace the
ADC774 in most circuits without additional changes. In
designs where the input to the ADS774 is changing rapidly
in the 200ns prior to a convert command, system perfor-
mance may be enhanced by delaying the convert command
by 200ns.
The Control Mode is provided to allow full use of the
internal sample/hold, eliminating the need for an external
sample/hold in most applications. As compared with sys-
tems using separate sample/hold and A/D, the ADS774 in
the Control Mode also eliminates the need for one of the
control signals, usually the convert command. The com-
mand that puts the internal sample/hold in the hold state
also initiates a conversion, reducing timing constraints in
many systems.
When using the ADS774 in the Emulation Mode to replace
existing converters in current designs, a sample/hold ampli-
fier often precedes the converter. In these cases, no addi-
tional delay in the convert command will be needed. The
existing sample/hold will not be slewing excessively when
going from the sample mode to the hold mode prior to a
conversion.
The basic difference between these two modes is the
assumptions about the state of the input signal both before
and during the conversion. The differences are shown in
Figure 9 and Table VI. In the Control Mode, it is assumed
that during the required 1.4µs acquisition time the signal is
not changing faster than the ADS774 can track. No assump-
In both modes, as soon as the conversion is completed the
internal sample/hold circuit immediately begins slewing to
track the input signal.
®
ADS774
10
BB [ BURR-BROWN CORPORATION ]
