ꢌ ꢒꢊ ꢗꢗ ꢁꢘ
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SBAS308A− MAY 2004 − REVISED MARCH 2005
95
90
85
80
75
70
65
µ
0.01 F
fIN = 70MHz
CLKP
ADS5542
CLKM
Differential Square Wave
or Sine Wave
(3VPP
SFDR
)
µ
0.01 F
Figure 44. AC-Coupled, Differential Clock Input
SNR
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 50%
duty cycle should be provided. Figure 45 shows the
performance variation of the ADC versus clock duty
cycle.
0
0.5
1.0
1.5
2.0
2.5
3.0
−
Differential Clock Amplitude
V
Figure 46. AC Performance vs Clock Amplitude
OUTPUT INFORMATION
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
100
fIN = 20MHz
SFDR
95
90
85
80
75
70
65
Two different output formats (straight offset binary or
two’s complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to put the outputs into a
high-impedance state.
SNR
40
45
50
55
60
−
Clock Duty Cycle
%
In the event of an input voltage overdrive, the digital
outputs go to the appropriate full-scale level. For a
positive overdrive, the output code is 0xFFF in straight
offset binary output format, and 0x7FF in 2’s
complement output format. For a negative input
overdrive, the output code is 0x000 in straight offset
binary output format, and 0x800 in 2’s complement
output format. These outputs to an overdrive signal are
ensured through design and characterization
Figure 45. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter will further
improve as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
amplitudes without exceeding the supply rails and
absolute maximum ratings of the ADC clock input.
Figure 46 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, refer to the ADS55xxEVM User’s Guide
(SLWU010), available for download from www.ti.com.
The output circuitry of the ADS5542, by design,
minimizes the noise produced by the data switching
transients, and, in particular, its coupling to the ADC
analog circuitry. Output D2 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
25
BB [ BURR-BROWN CORPORATION ]
