ADS5510
www.ti.com
SLAS499–JANUARY 2007
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 0x7FF in straight offset binary output format and 0x3FF in two's complement output
format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x400
in two's complement output format. These outputs to an overdrive signal are ensured through design and
characterization.
The output circuitry of the ADS5510, by design, minimizes the noise produced by the data switching transients,
and, in particular, its coupling to the ADC analog circuitry. Output D1 (pin 51) senses the load capacitance and
adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in
the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have
nearly the same load as D1 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply
voltage or temperature. Placing external resistors in series with the outputs is not recommended.
The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximum
sampling frequency. Table 5 and Table 6 show the setup, hold, input clock to output data delays, and rise and
fall times for different sampling frequencies with the DLL on and off, respectively.
Table 7 and Table 8 show the rise and fall times at additional sampling frequencies with DLL on and off,
respectively.
To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, td, that
results in the desired setup or hold time. Use either Equation 2or Equation 3 to calculate the value of td.
Desired setup time = td – tSTART
Desired hold time = tEND – td
Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
105
93
2.4
3.2
2.8
3.8
3.1
4.6
3.7
4.6
2.2
2.3
2.8
3.6
2.6
3.7
3.3
4.1
1.7
2.6
5.8
7.3
4.4
5.1
3.3
3.8
80
0.5
1.7
0.8
5.3
5.3
7.9
8.5
5.8
6.7
6.6
7.2
4.4
5.5
5.3
6.4
65
–0.5
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
tSETUP (ns)
tHOLD (ns)
tSTART (ns)
tEND (ns)
tr (ns)
tf (ns)
fS
(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80
65
40
20
10
2
3.2
4.3
8.5
17
4.2
5.7
11
1.8
2
3
3.8
2.8
5
4.5
1.5
2
8.4
8.3
11
5.8
6.6
7.5
7.5
6.6
7.2
8
4.4
5.5
7.3
7.6
5.3
6.4
7.8
8
3
11.8
14.5
21.6
31
2.6
2.5
4
3.5
4.7
6.5
19
–1
8.9
25.7
51
–9.8
-30
185
9.5
8
27
-3
11.5
515
284
370
8
320
576
50
82
75
150
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT Jitter,
Peak-to-Peak
tJIT (ps)
CLKOUT, Rise Time
tr (ns)
CLKOUT, Fall Time
tf (ns)
Input-to-Output Clock Delay
tPDI (ns)
fS
(MSPS)
MIN
TYP
2
MAX
MIN
TYP
1.7
2.1
2.6
MAX
MIN
TYP
175
210
260
MAX
250
315
380
MIN
4
TYP
4.7
4.3
4.1
MAX
5.5
105
80
2.2
2.8
3.5
1.8
2.3
2.9
2.5
3.1
3.7
3.5
5.1
65
4.8
24
Submit Documentation Feedback
BB [ BURR-BROWN CORPORATION ]
